Addressing redundant memory for lidar pixels
Techniques described herein provide memory redundancy. For example, the memory block for each pixel can be partitioned into multiple memory bins, and the number of memory bins can be larger than the number of time bins. Once a faulty memory cell is identified, an address associated with the memory bin that has the faulty memory cell can be skipped by an address generator. As such, the faulty memory cell is not used to store time-of-fight (ToF) information.
1 . A light ranging system comprising:
a light source configured to transmit pulse trains over a plurality of time intervals as part of an optical measurement, wherein each of the pulse trains includes one or more pulses from the light source and corresponds to a different time interval;
a photosensor comprising one or more photodetectors configured to detect photons of the pulse trains to generate a plurality of signals over the plurality of time intervals for each of the one or more photodetectors, wherein a signal from a photodetector indicates whether a photon was detected during a time bin of a time interval;
an accumulation circuit configured to receive, for each of a plurality of time bins in each of the plurality of time intervals, a set of signals from the one or more photodetectors and to aggregate a number of positive signals in the set of signals that indicate a detection of a photon, thereby generating a total signal count for the time bin for each time interval;
a memory block corresponding to the photosensor and configured to store the total signal count for each of the plurality of time bins, wherein the accumulation circuit updates the total signal counts for the plurality of time bins for each time interval, wherein the memory block is partitioned into a plurality of memory bins, each memory bin storing the total signal count for one of the plurality of time bins, and wherein the number of memory bins is larger than the number of time bins; and
an address generator configured to skip an address associated with a memory bin having a faulty memory cell.
2 . The light ranging system of claim 1 , wherein the one or more photodetectors are one or more single photon avalanche diodes (SPADs).
3 . The light ranging system of claim 1 , wherein the memory block is a static random-access memory (SRAM) block.
4 . The light ranging system of claim 1 , wherein the address generator skips the address associated with the memory bin having the faulty memory cell using a shift register.
5 . The light ranging system of claim 4 , wherein the shift register comprises a plurality of flip flops and a plurality of corresponding multiplexers, and wherein each flip flop is capable of being bypassed by its corresponding multiplexer.
6 . The light ranging system of claim 1 , wherein the address generator skips the address associated with the memory bin having the faulty memory cell using a counter.
7 . The light ranging system of claim 6 , wherein the address generator comprises:
the counter, wherein the counter is configured to generate a value starting from a programmable start position and increment by one in accordance with a clock signal until reaching a programmable stop position; and
a one-hot decoder configured to convert the value of the counter to an output address.
8 . The light ranging system of claim 7 , wherein the programmable start position corresponds to a succeeding address of the address associated with the memory bin having the faulty memory cell, and wherein the programmable stop position corresponds to a preceding address of the address associated with the memory bin having the faulty memory cell.
9 . The light ranging system of claim 1 , wherein the memory block comprises a plurality of parallel memory banks.
10 . The light ranging system of claim 1 , wherein the memory block comprises a single memory bank.
11 . A method of operating a light ranging system comprising:
transmitting, by a light source, pulse trains over a plurality of time intervals as part of an optical measurement, wherein each of the pulse trains includes one or more pulses from the light source and corresponds to a different time interval;
detecting, by a photosensor comprising one or more photodetectors, photons of the pulse trains to generate a plurality of signals over the plurality of time intervals for each of the one or more photodetectors, wherein a signal from a photodetector indicates whether a photon was detected during a time bin of a time interval;
receiving, by an accumulation circuit, for each of a plurality of time bins in each of the plurality of time intervals, a set of signals from the one or more photodetectors and to aggregate a number of positive signals in the set of signals that indicate a detection of a photon, thereby generating a total signal count for the time bin for each time interval; and
storing, by a memory block corresponding to the photosensor, the total signal count for each of the plurality of time bins, wherein the accumulation circuit updates the total signal counts for the plurality of time bins for each time interval, wherein the memory block is partitioned into a plurality of memory bins, each memory bin storing the total signal count for one of the plurality of time bins, and wherein the number of memory bins is larger than the number of time bins, and wherein an address associated with a first memory bin having a faulty memory cell is skipped by an address generator.
12 . The method of claim 11 , further comprising:
identifying the faulty memory cell in the memory block; and
determining the address associated with the faulty memory cell.
13 . The method of claim 12 , wherein the identifying the faulty memory cell in the memory block is based on testing the memory block.
14 . The method of claim 12 , wherein the determining the address associated with the faulty memory cell comprises:
determining the first memory bin associated with the faulty memory cell; and
determining the address associated with the faulty memory cell based on the first memory bin.
15 . The method of claim 11 , wherein the address associated with the first memory bin is skipped using a shift register in the address generator.
16 . The method of claim 15 , wherein the shift register comprises a plurality of flip flops and a plurality of corresponding multiplexers, and each flip flop is capable of being bypassed by its corresponding multiplexer.
17 . The method of claim 11 , wherein the address associated with the first memory bin is skipped by setting a multiplexer corresponding to the address associated with the faulty memory cell to bypass a corresponding flip flop in a shift register in the address generator.
18 . The method of claim 11 , wherein the address associated with the first memory bin is skipped using a counter in the address generator.
19 . The method of claim 11 , wherein the address associated with the first memory bin is skipped by:
setting a start position of a counter in the address generator, the start position corresponding to a succeeding address associated with the faulty memory cell; and
setting a stop position of the counter in the address generator, the stop position corresponding to a preceding address of the address associated with the faulty memory cell.
20 . The method of claim 19 , wherein the succeeding address is an immediately succeeding address, and the preceding address is an immediately preceding address.