Circuit to protect against multi-rail voltage glitching attacks

1 . A circuit comprising:

a bandgap circuit configured to generate a plurality of reference voltages;

a first voltage glitching detection circuit;

the first voltage glitching detection circuit configured to utilize a first one of the reference voltages and a first power rail voltage to generate a first reset signal in response to a voltage glitching attack on the first power rail;

a second voltage glitching detection circuit configured to operate independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first power rail;

a third voltage glitching detection circuit comprising:

a digital-to-analog converter configured to generate a plurality of digital-to-analog converter-generated reference voltages; and

a plurality of comparators configured to each receive at a first input a second power rail voltage, the comparators further configured to each receive at a second input one of the digital-to-analog converter-generated reference voltages.

2 . The circuit of claim 1 , wherein the second voltage glitching detection circuit comprises a self-referencing power-on detector for the first power rail.

3 . The circuit of claim 1 , wherein the power-on detector and bandgap circuit are configured to receive power from the first power rail.

4 . The circuit of claim 1 , wherein the first reset signal generated by the first voltage glitching detection circuit is a fine level reset signal.

5 . The circuit of claim 1 , wherein the second reset signal generated by the second voltage glitching detection circuit is a coarse level reset signal.

6 . The circuit of claim 1 , the first voltage glitching detection circuit comprising:

a comparator configured to receive at a first input the first one of the reference voltages from the bandgap circuit; and

the comparators configured to receive at a second input a scaled voltage from the first power rail.

7 . The circuit of claim 6 , wherein the power-on detector, bandgap circuit, and comparator are configured to receive power from the first power rail.

8 . The circuit of claim 1 , the third voltage glitching detection circuit utilizing a second one of the reference voltages and the second power rail voltage to generate a third reset signal in response to a voltage glitching attack on the second power rail.

9 . The circuit of claim 1 , wherein the digital-to-analog converter is programmable to generate the digital-to-analog converter-generated reference voltages in a window of a reference voltage received from the bandgap circuit.

10 . The circuit of claim 1 , wherein the power-on detector, bandgap circuit, and the third voltage glitching detection circuit are configured to receive power from the first power rail.

11 . A device comprising:

a system-on-a-chip configured to receive power from a first power rail;

a plurality of input-output devices configured to receive power from a second power rail;

a bandgap circuit configured to generate a plurality of reference voltages;

a first voltage glitching detection circuit configured to utilize a plurality of the reference voltages to generate a first reset signal in response to a voltage glitching attack on the first power rail;

a second voltage glitching detection circuit configured to utilize one of the plurality of reference voltages to generate a second reset signal in response to a voltage glitching attack on the second power rail;

a third voltage glitching detection circuit configured to operate independently of the reference voltages to generate a third reset signal in response to the voltage glitching attack on the second power rail; and

fourth voltage glitching detection circuit configured to utilize one of the plurality of reference voltages to generate a fourth reset signal in in response to a voltage glitching attack on a third power rail, the fourth voltage glitching detection circuit comprising:

a digital-to-analog converter configured to generate a plurality of digital-to-analog converter-generated reference voltages; and

a plurality of comparators configured to each receive at a first input a voltage from the third power rail, the comparators further configured to each receive at a second input one of the digital-to-analog converter-generated reference voltages.

12 . The device of claim 11 , wherein the third voltage glitching detection circuit comprises a self-referencing power-on detector for the second power rail.

13 . The device of claim 11 , wherein the second reset signal is a fine level reset signal.

14 . The device of claim 11 , wherein the third reset signal is a coarse level reset signal.

15 . The device of claim 11 , further comprising:

logic to form a combined reset signal from the second reset signal and the third reset signal.

16 . The circuit of claim 11 , the first voltage glitching detection circuit comprising:

logic configured to monitor a window of the first power rail voltage.

17 . A method comprising:

operating a bandgap circuit to generate a plurality of reference voltages;

applying a first one of the reference voltages and a first power rail voltage to a first voltage glitching detection circuit to generate a first reset signal in response to a voltage glitching attack on the first power rail;

operating a second voltage glitching detection circuit independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first power rail;

operating a third voltage glitching detection circuit by:

generating a plurality of additional reference voltages with a digital-to-analog converter;

applying a different one of the additional reference voltages at a first input to each of a plurality of comparators; and

applying a second power rail voltage to a second input to each of the comparators.