Quadrature error correction circuit and memory device having the same
The memory device includes a clock receiver receiving an external clock signal, a transmitter receiving first to Nth data in parallel and sequentially outputting the first to Nth data based on first to Nth clock signals including different phases, and a QEC circuit correcting a skew between the first to Nth clock signals, wherein the external clock signal includes a same frequency as the first to Nth clock signals, and the QEC circuit selectively receives the first clock signal among the first to Nth clock signals, generates the second clock signal including a phase different from a phase of the first clock signal based on a delay operation with respect to the first clock signal, and corrects the skew between the first to Nth clock signals by performing a phase comparison between the first to Nth clock signals generated based on the first and second clock signals.
1 . A memory device comprising:
a clock receiver configured to receive an external clock signal;
a transmitter configured to receive a plurality of data in parallel and sequentially output the plurality of data based on a plurality of clock signals having a same frequency as the external clock signal, each one of the plurality of clock signals having a phase different from another one of the plurality of clock signals; and
a quadrature error correction (QEC) circuit configured to:
receive only a first clock signal among the plurality of clock signals, the first clock signal having a first phase,
generate a second clock signal among the plurality of clock signals, based on a delay operation with respect to the first clock signal, the second clock signal having a second phase different from the first phase of the first clock signal, and
correct a skew between the plurality of clock signals by performing a phase comparison between the plurality of clock signals generated based on the first clock signal and the second clock signal.
2 . The memory device of claim 1 , wherein the plurality clock signals comprise the first clock signal, the second clock signal, a third clock signal and a fourth clock signal which have a sequential phase difference of 90 degrees in this order, and
wherein the QEC circuit comprises:
a first delayer configured to output the second clock signal by performing a first quad delay operation on the first clock signal;
a control code storage configured to store a first control code generated based on the phase comparison between the plurality of clock signals; and
an edge controller configured to receive the first clock signal and the second clock signal, and control at least one of a first rising edge and a first falling edge of the first clock signal and at least one of a second rising edge and a second falling edge of the second clock signal based on the first control code.
3 . The memory device of claim 2 , wherein the QEC circuit further comprises:
a phase splitter configured to output the first to fourth clock signals by performing a signal processing on the first clock signal and the second clock signal;
a multiplexer configured to selectively output two clock signals from among the first to fourth clock signals;
a second delayer configured to perform a second quad delay operation on one of the two clock signals output from the multiplexer; and
a phase detector configured to perform the phase comparison between a clock signal output from the multiplexer and a clock signal output from the second delayer, and output a comparison result.
4 . The memory device of claim 3 , further comprising:
a control code generator configured to generate the first control code based on the comparison result output from the phase detector,
wherein the first control code generated from the control code generator is stored in the control code storage.
5 . The memory device of claim 4 , wherein the control code generator is further configured to generate:
a second control code to control the first delayer to adjust a phase difference between the first clock signal and the second clock signal, and
a third control code to control the second quad delay operation on the one of the two clock signal output from the multiplexer by controlling the second delayer.
6 . The memory device of claim 3 , wherein the multiplexer is configured to: selectively output the first clock signal and the second clock signal in an operation of correcting the skew between the first clock signal and the second clock signal,
selectively output the second clock signal and the third clock signal in an operation of correcting the skew between the second clock signal and the third clock signal,
selectively output the third clock signal and the fourth clock signal in an operation of correcting the skew between the third clock signal and the fourth clock signal, and
selectively output the fourth clock signal and the first clock signal in an operation of correcting the skew between the fourth clock signal and the first clock signal.
7 . The memory device of claim 3 , wherein the phase detector comprises a Bang Bang Phase Detector.
8 . The memory device of claim 3 , further comprising:
a control code generator configured to generate a control code based on the comparison result output from the phase detector for correcting the skew between the plurality of clock signals.
9 . The memory device of claim 2 , wherein the QEC circuit further comprises:
a phase splitter configured to output the first to fourth clock signals by performing a signal processing on the first clock signal and the second clock signal;
a multiplexer configured to selectively output two clock signals from among the first to fourth clock signals;
at least one second delayer provided on a first path and configured to perform a second quad delay operation on one of the two clock signals output from the multiplexer;
at least one third delayer provided on a second path different from the first path and configured to perform a third quad delay operation on any one of the two clock signals output from the multiplexer; and
a phase detector configured to perform a phase comparison between the clock signal output from the multiplexer and a clock signal provided from the first path or the second path and provide a comparison result.
10 . The memory device of claim 9 , wherein, in a first operation, the multiplexer is further configured to output the two clock signals having a phase difference of 180 degrees from each other, and an even number of quad delay operations are performed on the clock signal provided via the second path,
wherein the phase detector is configured to perform a phase comparison between the clock signal output from the multiplexer and the clock signal provided from the second path; and
wherein, by controlling the first delayer based on a result of the phase comparison, the second clock signal is controlled to have a phase difference of 90 degrees relative to the first clock signal.
11 . The memory device of claim 10 , wherein, in a second operation, the multiplexer is further configured to output the two clock signals having a phase difference of 90 degrees from each other, and an odd number of quad delay operations are performed on the clock signal provided via the first path,
wherein the phase detector is configured to a phase comparison between the clock signal output from the multiplexer and the clock signal provided via the first path; and
wherein the skew between the first to fourth clock signals is corrected by controlling at least one of the first rising edge and the first falling edge of the first clock signal and at least one of the second rising edge and the second falling edge of the second clock signal based on a result of the phase comparison.
12 . The memory device of claim 1 , wherein the clock receiver is configured to receive a differential clock signal comprising the external clock signal and an inversion signal of the external clock signal.
13 . The memory device of claim 12 , wherein the plurality of clock signals comprise the first clock signal, the second clock signal, a third clock signal and a fourth clock signal which have a sequential phase difference of 90 degrees in this order, and
wherein the memory device further comprises:
a buffer configured to output the first clock signal and an inversion signal of the first clock signal based on a buffer operation on the differential clock signal;
a multiplexer configured to selectively output the first clock signal among the first clock signal and the inversion signal of the first clock signal; and
a phase locked loop configured to perform a phase locked loop operation on the first clock signal and provide the first clock signal to the QEC circuit.
14 . The memory device of claim 1 , wherein the external clock signal comprises a period divided by 4 compared to a data rate output by the transmitter.
15 . The memory device of claim 1 , wherein the QEC circuit further comprises:
a phase splitter configured to output the plurality of clock signals by performing a signal processing on the first clock signal and the second clock signal.
16 . The memory device of claim 15 , wherein the QEC circuit further comprises:
a phase detector configured to:
perform the phase comparison between two of the plurality of clock signals output by the phase splitter, and
output a comparison result of the phase comparison.
17 . A memory device comprising:
a clock receiver configured to receive an external clock signal;
a transmitter configured to receive a plurality of data in parallel and sequentially output the plurality of data based on a plurality of clock signals having a same frequency as the external clock signal, each one of the plurality of clock signals having a phase different from another one of the plurality of clock signals; and
a quadrature error correction (QEC) circuit configured to:
selectively receive a first clock signal among the plurality of clock signals, the first clock signal having a first phase,
generate a second clock signal based on a delay operation with respect to the first clock signal, the second clock signal having a second phase different from the first phase of the first clock signal, and
correct a skew between the plurality of clock signals by performing a phase comparison between the plurality of clock signals generated based on the first clock signal and second clock signal,
wherein the plurality clock signals comprise a first clock signal, a second clock signal, a third clock signal and a fourth clock signal which have a sequential phase difference of 90 degrees in this order, and
wherein the QEC circuit comprises:
a first delayer configured to output the second clock signal by performing a first quad delay operation on the first clock signal;
a control code storage configured to store a first control code generated based on the phase comparison between the plurality of clock signals; and
an edge controller configured to receive the first clock signal and the second clock signal, and control at least one of a first rising edge and a first falling edge of the first clock signal and at least one of a second rising edge and a second falling edge of the second clock signal based on the first control code.
18 . A memory device comprising:
a clock receiver configured to receive an external clock signal;
a transmitter configured to receive a plurality of data in parallel and sequentially output the plurality of data based on a plurality of clock signals having a same frequency as the external clock signal, each one of the plurality of clock signals having a phase different from another one of the plurality of clock signals; and
a quadrature error correction (QEC) circuit configured to:
selectively receive a first clock signal among the plurality of clock signals, the first clock signal having a first phase,
generate a second clock signal based on a delay operation with respect to the first clock signal, the second clock signal having a second phase different from the first phase of the first clock signal, and
correct a skew between the plurality of clock signals by performing a phase comparison between the plurality of clock signals generated based on the first clock signal and second clock signal,
wherein the clock receiver is configured to receive a differential clock signal comprising the external clock signal and an inversion signal of the external clock signal,
wherein the plurality of clock signals comprise the first clock signal, the second clock signal, a third clock signal and a fourth clock signal which have a sequential phase difference of 90 degrees in this order, and
wherein the memory device further comprises:
a buffer configured to output the first clock signal and an inversion signal of the first clock signal based on a buffer operation on the differential clock signal;
a multiplexer configured to selectively output the first clock signal among the first clock signal and the inversion signal of the first clock signal; and
a phase locked loop configured to perform a phase locked loop operation on the first clock signal and provide the first clock signal to the QEC circuit.