Flexible power management interface
Systems and methods are described for a flexible and selectable power management interface. The flexible and selectable power management interface can provide multiple power management interfaces which are selectable based on a selected processor IP core, a selected power management controller, and a variety of factors. The flexible and selectable power management interface can be a direct handshake hardware interface, a memory-mapped bus interface, or a combination of the direct handshake hardware interface and the memory-mapped bus interface.
1 . One or more non-transitory computer-readable storage media storing instructions that, upon execution by processing circuitry, cause operations comprising:
providing multiple power management interfaces for communication between a processor core and a power management controller, wherein a power management interface of the multiple power management interfaces has a type and is selected, based on a set of factors, from one of:
a direct handshake hardware interface;
a memory-mapped bus interface; and
a combination of the direct handshake hardware interface and the memory-mapped bus interface,
wherein the set of factors relates to an architecture of the processor core, and
wherein the processor core implements an interface to the power management controller independently of the type of the power management interface.
2 . The one or more non-transitory computer-readable storage media of claim 1 , wherein each one of the multiple power management interfaces is selected from one of the direct handshake hardware interface, the memory-mapped bus interface, or the combination of the direct handshake hardware interface and the memory-mapped bus interface.
3 . The one or more non-transitory computer-readable storage media of claim 2 , wherein registers are allocated based on the power management interface being the memory-mapped bus interface.
4 . The one or more non-transitory computer-readable storage media of claim 3 , wherein a first register is allocated in a power domain and a second register is allocated external to the power domain for use by the power management controller.
5 . The one or more non-transitory computer-readable storage media of claim 3 , wherein the communication between an internal controller of the processor core and the power management controller is based on a protocol that supports both the direct handshake hardware interface and the memory-mapped bus interface.
6 . The one or more non-transitory computer-readable storage media of claim 5 , wherein the protocol is used by the internal controller or the power management controller to initiate at least one of an idle power mode transition or an active mode transition at a power domain.
7 . The one or more non-transitory computer-readable storage media of claim 5 , wherein the power management controller is selected based on a power domain.
8 . A method comprising:
providing multiple power management interfaces for communication between a processor core and a power management controller, wherein a power management interface of the multiple power management interfaces has a type and is selected, based on a set of factors, from one of:
a direct handshake hardware interface;
a memory-mapped bus interface; and
a combination of the direct handshake hardware interface and the memory-mapped bus interface,
wherein the set of factors relates to an architecture of the processor core, and
wherein the processor core implements an interface to the power management controller independently of the type of the power management interface.
9 . The method of claim 8 , wherein the power management controller is external to the processor core, the processor core includes an internal controller, and the power management interface communicates between the power management controller and the internal controller.
10 . The method of claim 9 , further comprising:
providing registers when the memory-mapped bus interface is selected for communication between the internal controller and the power management controller.
11 . The method of claim 10 , wherein some of the registers are allocated in the processor core and some of the registers are allocated external to the processor core for use by the power management controller.
12 . The method of claim 10 , further comprising:
providing a protocol for communication between the internal controller and the power management controller which can work with both the direct handshake hardware interface and the memory-mapped bus interface.
13 . The method of claim 12 , wherein the protocol is used by the internal controller or the power management controller to initiate at least one of an idle power mode transition or an active power mode transition at the processor core.
14 . A processing system comprising:
at least one power domain;
a power management controller; and
a power management interface for communication between the at least one power domain and the power management controller, wherein the power management interface has a type that is selected, based on a set of factors, from one of:
a direct handshake hardware interface;
a memory-mapped bus interface; and p 2 a combination of the direct handshake hardware interface and the memory-mapped bus interface,
wherein the set of factors includes at least one of: a number of power domains, a power domain type, a power domain size, a power management mode, a level of power management control, a level of operational control, a level of performance control, or a power level, and
wherein the at least one power domain implements an interface to the power management controller independently of the type of the power management interface.
15 . The processing system of claim 14 , wherein the power management controller is external to the at least one power domain, the at least one power domain includes an internal controller, and the power management interface communicates between the power management controller and the internal controller.
16 . The processing system of claim 15 , further comprising:
registers configured to enable communications between the internal controller and the power management controller when the power management interface is a memory-mapped bus interface.
17 . The processing system of claim 16 , wherein some of the registers are allocated in the at least one power domain and some of the registers are allocated external to the at least one power domain for use by the power management controller.
18 . The processing system of claim 17 , further comprising:
a protocol for communication between the internal controller and the power management controller which is configured to work with both the direct handshake hardware interface and the memory-mapped bus interface.
19 . The processing system of claim 18 , wherein the protocol is used by the internal controller or the power management controller to initiate at least one of an idle power mode transition or an active power mode transition at a processor core.
20 . The processing system of claim 18 , wherein the at least one power domain and the power management controller are selectable.