IP Library › Granted Patent US 12,625,835
Granted Patent B2
US 12,625,835 · App. 18/761,834 · Granted May 12, 2026

Routing traffics having primary and secondary destinations in communication networks

Inventors: Kevin Safford (Fort Collins, CO); Victor Ruybalid (Beaverton, OR)
Assignee: Intel Corporation
G06F13/42H04L12/44H04L45/02H04L45/16H04L45/48H04L49/109G06F2213/0038
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Quick Facts
Patent No.
US 12,625,835
App. No.
18/761,834
Granted
May 12, 2026
Kind
B2
Abstract

Embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. A routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. The control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. Otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. Other embodiments may also be described and claimed.

Claims (39)

1 . An electronic device comprising:

an input port;

a primary output port;

a secondary output port; and

control circuitry configured to:

identify a message received via the input port, the message related to debug trace information of a chip;

identify a destination identifier in the message;

identify a functional state of the secondary output port;

if the secondary output port is in a functional state, then identify, based on the destination identifier, whether to output the message via the primary output port or the secondary output port; and

if the secondary output port is not in a functional state, then output the message via the primary output port.

2 . The electronic device of claim 1 , wherein the destination identifier is a binary identifier with a first value and a second value.

3 . The electronic device of claim 2 , wherein the destination identifier is a single bit.

4 . The electronic device of claim 2 , wherein the first value indicates that the control circuitry is to output the message via the primary output port, and wherein the second value indicates that the control circuitry is to output the message via the secondary output port.

5 . The electronic device of claim 4 , wherein the control circuitry is configured to output the message via the primary output port if the secondary output port is not in a functional state and the destination identifier is the second value.

6 . The electronic device of claim 1 , wherein the electronic device is an arbiter of a debug trace fabric of the chip.

7 . The electronic device of claim 1 , wherein the secondary output port is not in a functional state if the secondary output port is in a not connected state, a configuration state, or a reset state.

8 . The electronic device of claim 1 , wherein the control circuitry is configured to output the message via the primary output port and the secondary output port without modification to the destination identifier.

9 . One or more non-transitory computer-readable media (NTCRM) comprising instructions that, when executed, are to cause an arbiter of a debug trace fabric of a chip to:

identify a message received via an input port of the arbiter;

identify a destination identifier in the message;

identify a functional state of a secondary output port of the arbiter;

if the secondary output port is in a functional state, then identify, based on the destination identifier, whether to output the message via a primary output port of the arbiter or the secondary output port; and

if the secondary output port is not in a functional state, then output the message via the primary output port.

10 . The one or more NTCRM of claim 9 , wherein the destination identifier is a binary identifier with a first value and a second value.

11 . The one or more NTCRM of claim 10 , wherein the first value indicates that the arbiter is to output the message via the primary output port, and wherein the second value indicates that the arbiter is to output the message via the secondary output port.

12 . The one or more NTCRM of claim 11 , wherein the arbiter is configured to output the message via the primary port if the secondary output port is not in a functional state and the destination identifier is the second value.

13 . The one or more NTCRM of claim 9 , wherein the secondary output port is not in a functional state if the secondary output port is in a not connected state, a configuration state, or a reset state.

14 . The one or more NTCRM of claim 9 , wherein the arbiter is configured to output the message via the primary output port and the secondary output port without modification to the destination identifier.

15 . A chip comprising:

a debug trace fabric encoder configured to generate a message related to debug trace information of the chip, wherein the message includes a destination identifier; and

an arbiter configured to:

identify the message received from the debug trace fabric encoder via an input port of the arbiter;

identify a functional state of a secondary output port of the arbiter;

if the secondary output port is in a functional state, then identify, based on the destination identifier, whether to output the message via a primary output port of the arbiter or the secondary output port; and

if the secondary output port is not in a functional state, then output the message via the primary output port.

16 . The chip of claim 15 , wherein the destination identifier is a single-bit binary identifier with a first value and a second value.

17 . The chip of claim 16 , wherein the first value indicates that the arbiter is to output the message via the primary output port, and wherein the second value indicates that the arbiter is to output the message via the secondary output port.

18 . The chip of claim 17 , wherein the arbiter is configured to output the message via the primary port if the secondary output port is not in a functional state and the destination identifier is the second value.

19 . The chip of claim 15 , wherein the arbiter is configured to output the message via the primary output port and the secondary output port without modification to the destination identifier.

Continuity (2)
Continuation 16876902 · May 18, 2020
Related Publication 20240356868A1 · Oct 24, 2024
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