Systems and methods for configuring a display device and display system
Displays, systems, and methods may be utilized in applications including, but not limited to, projectors, head-up displays, and augmented reality (AR), mixed reality (MR), and virtual reality (VR) systems or devices, such as headsets or other near-eye devices or systems. Tiled or Tile-able displays and methods, in accordance with the present invention, provide displays of varying sizes, and as such, a Tiled or Tile-able display is configured to accommodate the display size needed for various wearable and mobile devices that require or incorporate displays.
1 . A display device, comprising:
a plurality of tiles arranged in an array on a printed circuit board (PCB), the PCB configured to electrically couple the plurality of tiles, each tile comprising:
an illumination die comprising at least one illuminating element; and
a tile-able backplane die comprising:
pixel logic circuitry at least one of arranged on, embedded in, integrated into, formed on, deposited onto or coupled to a first area of a backplane die; and
input/output logic circuitry at least one of arranged on, embedded in, integrated into, formed on, deposited onto or coupled to a second area of the backplane die;
wherein the illumination die is coupled to a front surface of the tile-able backplane die such that the first area is aligned with at least one illuminating element in the illumination die; and
wherein each respective tile is coupled to the printed circuit board through a plurality of openings in a back surface of the respective tile-able backplane die, the plurality of openings in the back surface aligned with the second area of the backplane die.
2 . The display device of claim 1 , wherein:
the first area comprises a first strip area; and
the second area comprises a second strip area.
3 . The display device of claim 1 , wherein:
the first area comprises a plurality of first strip areas; and
the second area comprises a plurality of second strip areas alternating with the plurality of first strip areas.
4 . The display device of claim 1 , wherein the PCB electrically couples the plurality of tiles in series.
5 . The display device of claim 1 , wherein image or video data is being sent to the input/output logic circuitry of a tile for display in a next frame while image or video data for a current frame is being displayed on the illumination die of the tile.
6 . The display device of claim 1 , wherein:
each tile of the plurality of tiles has a corresponding tile address;
the PCB comprises a master controller coupled to at least one of the tiles in the plurality of tiles;
the master controller sends data to the tile to which it is coupled, the data having a header including a tile address identifier;
the backplane device of a tile identifies tile data in the data received from the master controller, the tile data being a subset of the data sent from the master controller; and
the backplane device of the tile associated with the tile address identifier stores the tile data at a memory component in, or associated with, the tile.
7 . The display device of claim 6 , wherein:
the master controller receives data from a first device of a first format; and
the master controller converts the data to a second format that can be read or processed by the backplane device of a tile.
8 . The display device of claim 7 , wherein:
the first device is a device that outputs image data.
9 . The display device of claim 7 , wherein:
each illumination element of an illumination die is coupled to a first storage device and a second storage device.
10 . A display system comprising:
a pixel array of pixels, each pixel having at least one illuminating element in an illumination die, each illumination element of a pixel being electrically coupled to pixel circuitry in a tile-able backplane die of a tile, the tile-able backplane die comprising:
pixel drive and logic circuitry on a first area of the backplane die comprising:
a receiving pixel memory device;
an active pixel memory device electrically coupled to the receiving pixel memory device;
logic function circuitry coupled to the active pixel memory device;
a latch coupled to the logic function circuitry; and
a current drive device coupled to the latch, wherein the current drive device drives operation of each pixel of the pixel array; and
tile controller circuitry on a second area of the backplane die comprising circuitry configured to:
receive a serial data stream;
extract image data or video data from the serial data stream according to when an address of the tile is in the data stream;
decode the image or video data after it has been extracted from the data stream;
control writing of the image or video data to the receiving pixel memory device; and
write the image data or video data that has been extracted and subsequently decoded to a data bus corresponding to or associated with a column that includes or contains one or more pixels of the pixel array, the column being identified as a destination for writing the image data or video data;
wherein the illumination die is coupled to a front surface of the tile-able backplane die such that the first area is aligned with at least one illuminating element in the illumination die,
wherein the tile-able backplane die comprises a plurality of openings in a back surface of the tile-able backplane die, the plurality of openings configured to receive the serial data stream from a tile array controller.
11 . The display system of claim 10 , wherein:
the first area comprises a first strip area; and
the second area comprises a second strip area.
12 . The display system of claim 10 , wherein:
the control logic circuitry writes a respective plurality of portions of the image data or video data that has been extracted and subsequently decoded to each of a plurality of data buses corresponding to or associated with a plurality of columns that each include or contain one or more pixels of the pixel array, each column being identified as a destination for writing a respective one of the plurality of portions of the image data or video data;
the first area comprises a plurality of first strip areas; and
the second area comprises a plurality of second strip areas alternating with the plurality of first strip areas.
13 . The display system of claim 10 , wherein the at least one illuminating element of a pixel comprises three illuminating elements generating three colors of light.
14 . The display system of claim 10 , wherein the tile controller circuitry is configured to output a ROW/WRITE signal to a row of the pixels that have been identified to receive the extracted and subsequently decoded data.
15 . The display system of claim 14 , wherein the tile controller circuitry is configured to output a LOAD output signal that initiates transfer of data from the receiving pixel memory device to the active pixel memory device.
16 . The display system of claim 15 , further comprising:
a time-varying value (TVV) generator, wherein after the data has been transferred to the active pixel memory device, a display cycle begins, wherein during the display cycle, the TVV generator provides a changing value or voltage on a TVV bus which the pixel circuitry combines with the value or voltage in the active pixel memory device, and produces a time-varying voltage that is used to modulate a current driver device electrically coupled to a master pixel of the pixel array.
17 . The display system of claim 10 , wherein the at least one illuminating element of a pixel comprises at least one LED.
18 . The display system of claim 17 , wherein the at least one LED is at least one microLED.
19 . A method, comprising:
transmitting serial data from a master controller to one or more tiles in a plurality of tiles via a printed circuit board, the data having a header including a tile address, the tile address being associated with a first tile of the plurality of tiles;
receiving the serial data at a tile controller of the first tile, the tile controller comprising a backplane, the backplane comprising:
a first area comprising a plurality of first strip areas;
a second area comprising a plurality of second strip areas alternating with the plurality of first strip areas;
pixel logic circuitry at least one of arranged on, embedded in, integrated into, formed on, deposited onto or coupled to the first area, the pixel logic circuitry being coupled to one or more illumination elements in an illumination die coupled to a front surface of the backplane; and
input/output logic circuitry at least one of arranged on, embedded in, integrated into, formed on, deposited onto or coupled to the second area, the input/output logic circuitry being coupled to the printed circuit board through a plurality of openings in a back surface of the backplane aligned with the second area; and
at the tile controller of the first tile:
recognizing the tile address in the header of the serial data;
identifying tile data as a subset of the serial data received from the master controller; and
storing the tile data at a memory component in, or associated with, the first tile.
20 . The method of claim 19 , further comprising:
receiving, at the master controller, image data of a first format; and
converting, at the master controller, the image data from the first format to a serial format to arrive at the serial data.