Granted Patent B2

US 12,315,418 · App. 18/066,725 · Granted May 27, 2025

Inventors: Kapil V. Sakariya (Los Altos, CA); Tore Nauta (Santa Cruz, CA); Hopil Bae (Sunnyvale, CA); Henry C. Jen (Los Altos, CA); James E. Pedder (Cupertino, CA); Sunggu Kang (San Jose, CA); Shingo Hatanaka (San Jose, CA); Xiang Lu (Campbell, CA); Mahdi Farrokh Baroughi (Santa Clara, CA); Hasan Akyol (Mountain View, CA); Saif Choudhary (San Jose, CA); Ion Bita (Santa Clara, CA)

G09G3/2088G09G3/2014G09G3/32G09G2300/0413G09G2300/0426G09G2300/0804G09G2300/0857G09G2310/027G09G2310/0272G09G2310/0291G09G2310/08G09G2330/08

Abstract

Claims (19)

1. A display panel comprising:

an array of driver chips arranged in rows and columns, each driver chip including digital logic coupled with analog circuitry that includes a plurality of switches and plurality of current sources;

wherein each driver chip is connected with a corresponding plurality of light emitting diodes (LEDs) forming a plurality of pixels;

wherein each pixel includes a plurality of subpixels, each subpixel including a primary LED connected to a corresponding driver chip and a spare LED connected to the corresponding driver chip; and

wherein the primary LED and the spare LED are coupled to a common switch of the plurality of switches of the driver chip, the common switch is coupled to a common current source of the plurality of current sources that corresponds to the common switch, and the common switch is a transistor that causes the common current source to illuminate either the primary LED or the spare LED;

wherein the digital logic includes a counter, a plurality of comparators, and a register; wherein the common switch is coupled to a common comparator of the plurality of comparators.

2. The display panel of claim 1 , wherein the primary LED is electrically connected with a first electrode line, and the spare LED is electrically connected with a spare electrode line.

3. The display panel of claim 2 , wherein the first electrode line and the spare electrode line are connected with a weld.

4. The display panel of claim 2 , further comprising a common cathode line formed on top of and in electrical connection with the primary LED and the spare LED.

5. The display panel of claim 4 , wherein the common cathode line is connected to the plurality of pixels.

6. The display panel of claim 2 , wherein each LED has a maximum lateral dimension of 1 to 20 μm.

7. The display panel of claim 2 , wherein each LED is bonded to the display panel with a solder bump.

8. The display panel of claim 2 , wherein the primary LEDs for each pixel are in a same row.

9. The display panel of claim 2 , wherein the primary LEDs and the spare LEDs for each pixel are staggered.

10. The display panel of claim 1 , wherein each pixel driver chip includes a reference voltage input.

11. The display panel of claim 1 , wherein each pixel driver chip includes a plurality of reference voltage inputs for the plurality of subpixels.

12. The display panel of claim 2 , wherein the transistor is a silicon metal-oxide-semiconductor-field-effect-transistor (MOSFET) transistor.

13. The display panel of claim 1 , wherein the digital logic includes a digital storage element to store video data.

14. The display panel of claim 1 , wherein the digital logic receives digital video data for output via the analog circuitry.

Continuity (5)

References Cited (61)