Gate driver and display apparatus including the same
A gate driver includes a plurality of stages. A stage of the stages includes a pull-up circuit which applies a high voltage to an output node which outputs a gate signal, a pull-down circuit which applies a low voltage lower than the high voltage to the output node, a gate signal control circuit which controls the pull-up circuit and the pull-down circuit, and a stabilization transistor connected to the pull-down circuit. The stabilization transistor is turned off when the gate signal has the low voltage.
1 . A display apparatus comprising:
a display panel including a pixel;
a gate driver which outputs a gate signal to the display panel; and
a data driver which applies a data voltage to the display panel,
wherein the gate driver includes a plurality of stages,
wherein a stage of the stages includes:
a pull-up circuit which applies a high voltage to an output node which outputs the gate signal;
a pull-down circuit which applies a low voltage lower than the high voltage to the output node;
a gate signal control circuit which controls the pull-up circuit and the pull-down circuit; and
a stabilization transistor connected to the pull-down circuit,
wherein the pixel emits light based on the data voltage of a current frame during a first frame and emits light based on the data voltage of a previous frame during a second frame,
wherein the stabilization transistor is turned off during a self-scan period included in the second frame and a control electrode of the stabilization transistor receives a power voltage that has a first voltage in an address period included in the first frame and a second voltage in the self-scan period, wherein the second voltage is lower than the low voltage, and
wherein the gate signal control circuit includes:
a first transistor including a control electrode which receives a clock signal, a first electrode which receives a previous stage gate signal or a vertical start signal and a second electrode connected to a first node;
a second transistor including a control electrode connected to the first node, a first electrode which receives the high voltage and a second electrode connected to a second node;
a third transistor including a control electrode which receives the low voltage, a first electrode connected to the first node and a second electrode connected to a third node;
a fourth transistor including a control electrode connected to a fourth node, a first electrode which receives the low voltage and a second electrode connected to the second node.
2 . The display apparatus of claim 1 , wherein the stabilization transistor is an N-type transistor.
3 . The display apparatus of claim 1 , wherein the stabilization transistor includes a control electrode which receives a power voltage, a first electrode connected to the gate signal control circuit and a second electrode connected to the pull-down circuit.
4 . The display apparatus of claim 1 , wherein an absolute value of the second voltage is about twice an absolute value of the low voltage.
5 . The display apparatus of claim 1 , wherein the pull-up circuit includes a fifth transistor including a control electrode connected to the second node, a first electrode which receives the high voltage and a second electrode connected to the output node, and
wherein the pull-down circuit includes a sixth transistor including a control electrode connected to the fourth node, a first electrode which receives the low voltage and a second electrode connected to the output node.
6 . The display apparatus of claim 5 , wherein the stabilization transistor includes a control electrode which receives a power voltage, a first electrode connected to the third node and a second electrode connected to the fourth node.
7 . The display apparatus of claim 1 , wherein the first electrode of the first transistor receives the vertical start signal.
8 . A display apparatus comprising:
a display panel including a pixel;
a gate driver which outputs a gate signal to the display panel; and
a data driver which applies a data voltage to the display panel,
wherein the gate driver includes a plurality of stages,
wherein a stage of the stages includes:
a pull-up circuit which applies a high voltage to an output node which outputs the gate signal;
a pull-down circuit which applies a low voltage lower than the high voltage to the output node;
a gate signal control circuit which controls the pull-up circuit and the pull-down circuit; and
a stabilization transistor connected to the pull-down circuit,
wherein the stabilization transistor is turned off during a blank period in which the data voltage is not applied to the pixel, and a control electrode of the stabilization transistor receives a power voltage that has a first voltage in an address period included in the first frame and a second voltage in the self-scan period, wherein the second voltage is lower than the low voltage, and
wherein the gate signal control circuit includes:
a first transistor including a control electrode which receives a clock signal, a first electrode which receives a previous stage gate signal or a vertical start signal and a second electrode connected to a first node;
a second transistor including a control electrode connected to the first node, a first electrode which receives the high voltage and a second electrode connected to a second node;
a third transistor including a control electrode which receives the low voltage, a first electrode connected to the first node and a second electrode connected to a third node;
a fourth transistor including a control electrode connected to a fourth node, a first electrode which receives the low voltage and a second electrode connected to the second node.
9 . The display apparatus of claim 8 , wherein the stabilization transistor is an N-type transistor.
10 . The display apparatus of claim 8 , wherein the stabilization transistor includes a control electrode which receives a power voltage, a first electrode connected to the gate signal control circuit and a second electrode connected to the pull-down circuit.
11 . A gate driver comprising:
a plurality of stages,
wherein a stage of the stages includes,
a pull-up circuit which applies a high voltage to an output node which outputs a gate signal;
a pull-down circuit which applies a low voltage lower than the high voltage to the output node;
a gate signal control circuit which controls the pull-up circuit and the pull-down circuit; and
a stabilization transistor connected to the pull-down circuit,
wherein the stabilization transistor is turned off when the gate signal has the low voltage, and a control electrode of the stabilization transistor receives a power voltage that has a first voltage in an address period included in the first frame and a second voltage in the self-scan period, wherein the second voltage is lower than the low voltage, and
wherein the gate signal control circuit includes:
a first transistor including a control electrode which receives a clock signal, a first electrode which receives a previous stage gate signal or a vertical start signal and a second electrode connected to a first node;
a second transistor including a control electrode connected to the first node, a first electrode which receives the high voltage and a second electrode connected to a second node;
a third transistor including a control electrode which receives the low voltage, a first electrode connected to the first node and a second electrode connected to a third node;
a fourth transistor including a control electrode connected to a fourth node, a first electrode which receives the low voltage and a second electrode connected to the second node.
12 . The gate driver of claim 11 , wherein the stabilization transistor is an N-type transistor.
13 . The gate driver of claim 11 , wherein the stabilization transistor includes a control electrode which receives a power voltage, a first electrode connected to the gate signal control circuit and a second electrode connected to the pull-down circuit.
14 . An electronic apparatus comprising:
a display panel including a pixel;
a gate driver which outputs a gate signal to the display panel;
a data driver which applies a data voltage to the display panel;
a driving controller which controls the gate driver and the data driver based on an input control signal; and
a processor which outputs the input control signal,
wherein the gate driver includes a plurality of stages,
wherein a stage of the stages includes:
a pull-up circuit which applies a high voltage to an output node which outputs the gate signal;
a pull-down circuit which applies a low voltage lower than the high voltage to the output node;
a gate signal control circuit which controls the pull-up circuit and the pull-down circuit; and
a stabilization transistor connected to the pull-down circuit,
wherein the pixel emits light based on the data voltage of a current frame during a first frame and emits light based on the data voltage of a previous frame during a second frame,
wherein the stabilization transistor is turned off during a self-scan period included in the second frame, and a control electrode of the stabilization transistor receives a power voltage that has a first voltage in an address period included in the first frame and a second voltage in the self-scan period, wherein the second voltage is lower than the low voltage, and
wherein the gate signal control circuit includes:
a first transistor including a control electrode which receives a clock signal, a first electrode which receives a previous stage gate signal or a vertical start signal and a second electrode connected to a first node;
a second transistor including a control electrode connected to the first node, a first electrode which receives the high voltage and a second electrode connected to a second node;
a third transistor including a control electrode which receives the low voltage, a first electrode connected to the first node and a second electrode connected to a third node;
a fourth transistor including a control electrode connected to a fourth node, a first electrode which receives the low voltage and a second electrode connected to the second node.