Sense amplifier and method of operation thereof
A sense amplifier that senses and amplifies data stored in a memory cell includes a first sampling circuit that performs a sampling operation based on a first current, a second sampling circuit that performs a sampling operation based on a second current, and a sense amplification circuit configured to generate an offset compensation voltage that compensates for an offset between a first data output node and a second data output node through an offset compensation operation. Data stored in the memory cell may be read based on the magnitude of the current received from the memory cell, and the sensing time utilized to read data stored in the memory cell may be shortened.
1 . A sense amplifier that senses and amplifies data stored in a memory cell, the sense amplifier comprising:
a first sampling circuit including a first bit line capacitor connected to a bit line, a first sampling transistor connected between the bit line and a first sampling node, and a first decoupling capacitor connected between the first sampling node and a first data output node, wherein the first sampling circuit is configured to receive a first current through the bit line;
a second sampling circuit including a second bit line capacitor connected to a complementary bit line, a second sampling transistor connected between the complementary bit line and a second sampling node, and a second decoupling capacitor connected between the second sampling node and a second data output node, wherein the second sampling circuit is configured to receive a second current through the complementary bit line; and
a sense amplification circuit connected between the first data output node and the second data output node and configured to generate an offset compensation voltage that compensates for an offset between the first data output node and the second data output node through an offset compensation operation, wherein
the first sampling circuit is configured to provide, to the first data output node, a sampling voltage generated by performing a sampling operation based on a sampling control signal, and
the sense amplification circuit performs the offset compensation operation while the first sampling circuit performs the sampling operation.
2 . The sense amplifier of claim 1 , wherein a magnitude of the offset compensation voltage corresponds to a difference between voltages at the second data output node and the first data output node when a logic level of the sampling control signal is in a rising edge.
3 . The sense amplifier of claim 1 , wherein a magnitude of the sampling voltage corresponds to a difference between voltages of the bit line and the complementary bit line when a logic level of the sampling control signal is in a rising edge.
4 . The sense amplifier of claim 1 , wherein the sense amplification circuit performs a sensing operation that senses data stored in the memory cell based on a difference between voltages at the first data output node and the second data output node when a logic level of the sampling control signal is in a falling edge, and the difference between the voltages at the first data output node and the second data output node corresponds to a sum of the offset compensation voltage and the sampling voltage.
5 . The sense amplifier of claim 4 , wherein, when the sense amplification circuit performs the sensing operation, both a first end and a second end of the first sampling transistor are not electrically connected to each other.
6 . The sense amplifier of claim 1 , wherein, when data stored in the memory cell has a first value, the first current is greater than the second current, and when the data stored in the memory cell has a second value, the first current is less than the second current.
7 . The sense amplifier of claim 1 , wherein the sense amplification circuit further comprises a precharge equalizing transistor configured to provide a precharge voltage to the sense amplification circuit based on a precharge equalizing signal, and to provide the precharge voltage to the first data output node and the second data output node.
8 . The sense amplifier of claim 7 , further comprising:
a first precharge transistor electrically connected to the first data output node and the first sampling node; and
a second precharge transistor electrically connected to the second data output node and the second sampling node, wherein
the first precharge transistor provides the precharge voltage to the first sampling node, and
the second precharge transistor provides the precharge voltage to the second sampling node.
9 . A sense amplifier that senses and amplifies data stored in a memory cell, the sense amplifier comprising:
a first sampling circuit including a first bit line capacitor connected to a bit line, a first sampling transistor connected between the bit line and a first sampling node, and a first decoupling capacitor connected between the first sampling node and a first data output node, and configured to receive a first current through the bit line;
a second sampling circuit including a second bit line capacitor connected to a complementary bit line, a second sampling transistor connected between the complementary bit line and a second sampling node, and a second decoupling capacitor connected between the second sampling node and a second data output node, and configured to receive a second current through the complementary bit line; and
a first precharge transistor connected to the first sampling node and configured to provide a first precharge voltage to the first sampling node based on a precharge transistor control signal;
a second precharge transistor connected to the second sampling node and configured to provide the first precharge voltage to the second sampling node based on the precharge transistor control signal; and
a sense amplification circuit connected between the first data output node and the second data output node and configured to generate an offset compensation voltage that compensates for an offset between the first data output node and the second data output node through an offset compensation operation, wherein
the first sampling circuit is configured to provide, to the first data output node, a sampling voltage generated by performing a sampling operation based on a sampling control signal, and
the sense amplification circuit performs the offset compensation operation while the first sampling circuit performs the sampling operation.
10 . The sense amplifier of claim 9 , wherein a magnitude of the offset compensation voltage corresponds to a difference between voltages at the second data output node and the first data output node when a logic level of the sampling control signal is in a rising edge.
11 . The sense amplifier of claim 9 , wherein a magnitude of the sampling voltage corresponds to a difference between voltages of the bit line and the complementary bit line when a logic level of the sampling control signal is in a rising edge.
12 . The sense amplifier of claim 9 , wherein the sense amplification circuit performs a sensing operation that senses data stored in the memory cell based on a difference between voltages at the first data output node and the second data output node when a logic level of the sampling control signal is in a falling edge, and the difference between the voltages at the first data output node and the second data output node corresponds to a sum of the offset compensation voltage and the sampling voltage.
13 . The sense amplifier of claim 12 , wherein, when the sense amplification circuit performs the sensing operation, both a first end and a second end of the first sampling transistor are not electrically connected to each other.
14 . The sense amplifier of claim 12 , wherein, when data stored in the memory cell has a first value, the first current is greater than the second current, and when the data stored in the memory cell has a second value, the first current is less than the second current.
15 . The sense amplifier of claim 12 , wherein the sense amplification circuit further comprises a precharge equalizing transistor configured to provide a second precharge voltage to the sense amplification circuit based on a precharge equalizing signal, and to provide the second precharge voltage to the first data output node and the second data output node.
16 . The sense amplifier of claim 15 , wherein the first precharge voltage is greater than the second precharge voltage.
17 . A method of operating a sense amplifier that senses and amplifies data stored in a memory cell, wherein
the sense amplifier includes a first sampling circuit connected to a bit line, a second sampling circuit connected to a complementary bit line, and a sense amplification circuit connected between a first data output node and a second data output node, the method comprising:
generating an offset compensation voltage that compensates for an offset between the first data output node and the second data output node;
generating a sampling voltage corresponding to a voltage difference between the bit line and the complementary bit line;
providing the sampling voltage to the first data output node based on a sampling control signal;
performing a sensing operation of sensing data stored in the memory cell based on a difference between voltages of the first data output node and the second data output node; and
performing a precharge operation by applying a precharge voltage to the sense amplifier.
18 . The method of claim 17 , wherein a magnitude of the offset compensation voltage corresponds to a difference between voltages at the second data output node and the first data output node when a logic level of the sampling control signal is in a rising edge.
19 . The method of claim 18 , wherein a magnitude of the sampling voltage corresponds to a difference between voltages of the bit line and the complementary bit line when the logic level of the sampling control signal is in the rising edge.
20 . The method of claim 17 , wherein
a first current is provided to the first sampling circuit through the bit line,
a second current is provided to the second sampling circuit through the complementary bit line,
when data stored in the memory cell has a first value, the first current is greater than the second current, and
when the data stored in the memory cell has a second value, the first current is less than the second current.