IP Library › Granted Patent US 12,627,216
Granted Patent B2
US 12,627,216 · App. 17/942,535 · Granted May 12, 2026

Driving circuit for switching elements with controllable driving current

Inventor: Shusuke Kawai (Yokohama Kanagawa, JP)
Assignees: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
H02M1/08H02M7/5387H02P27/06H03K17/0822
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Quick Facts
Patent No.
US 12,627,216
App. No.
17/942,535
Granted
May 12, 2026
Kind
B2
Abstract

In one embodiment, electronic circuitry includes a driving circuit that is configured to: supply a driving current to a control terminal of a first switching element; and increase the driving current in accordance with a first time at which a current flowing through a second switching element connected to a first terminal or a second terminal of the first switching element becomes 0.

Claims (61)

1 . An electronic circuitry comprising:

a driving circuit configured to:

supply a driving current to a control terminal of a first switching element; and

increase the driving current in accordance with a first time, the first time being when a current flowing through a second switching element becomes 0, the second switching element being connected to a first terminal or a second terminal of the first switching element, wherein

the driving circuit increases the driving current of the first switching element in a first period according to the first time, the first period being before or after the first time, and

the first period is determined based on a parasitic capacitance of the first switching element, a parasitic capacitance of the second switching element and a parasitic inductance of wiring that connects the first switching element and the second switching element.

2 . The electronic circuitry according to claim 1 , wherein

the driving circuit increases the driving current of the first switching element in a step-like manner in the first period, and

a target value of the driving current is determined based on:

a drain parasitic capacitance of the first switching element;

a gate parasitic capacitance of the first switching element;

a transconductance of the first switching element;

the parasitic inductance of the wiring that connects the first switching element and the second switching element; and

a voltage across the parasitic inductance at the first time.

3 . The electronic circuitry according to claim 1 , wherein

the driving circuit reduces the driving current of the first switching element in a second period, the second period being between the first time and a second time, the second time being when a current flowing through the first switching element starts to increase.

4 . The electronic circuitry according to claim 3 , wherein

the driving circuit reduces the driving current of the first switching element in a step-like manner in the second period, and

a target value of the driving current is a value that causes the voltage across a parasitic inductance of wiring that connects the first switching element and the second switching element at the first time to be reduced by a predetermined percentage in comparison with a case where the driving current is not reduced.

5 . The electronic circuitry according to claim 4 , wherein

the driving circuit reduces the driving current of the first switching element in a step-like manner over a plurality of times in the second period.

6 . The electronic circuitry according to claim 4 , wherein

the driving circuit increases the driving current of the first switching element in a step-like manner at least once in reducing the driving current in a step-like manner in the second period.

7 . An electronic system, comprising:

the electronic circuitry according to claim 1 ; and

a control circuit configured to provide waveform information of the driving current to the driving circuit of the electronic circuitry, wherein

the driving circuit generates the driving current based on the waveform information.

8 . The electronic system according to claim 7 , wherein

the control circuit includes:

a detection circuit configured to detect an operating state of the first switching element;

a storage device configured to store a plurality of waveform information of the driving current; and

a selection circuit configured to select one waveform information of the driving current from the storage device, based on the operating state of the first switching element, the operating state being detected by the detection circuit.

9 . An electronic circuitry, comprising:

a driving circuit configured to:

supply a driving current to a control terminal of a first switching element; and

reduce the driving current of the first switching element in a second period between a first time and a second time, the first time being when a current flowing through a second switching element becomes 0, the second switching element being connected to a first terminal or a second terminal of the first switching element, the second time being when a current flowing through the first switching element starts increasing, wherein

the driving circuit reduces the driving current of the first switching element in a step-like manner in the second period, and

a target value of the driving current is a value that causes a voltage across a parasitic inductance of wiring at the first time to be reduced by a predetermined percentage in comparison with a case where the driving current is not reduced, the wiring connecting the first switching element and the second switching element.

10 . The electronic circuitry according to claim 9 , wherein

the driving circuit reduces the driving current of the first switching element in a step-like manner over a plurality of times in the second period.

11 . The electronic circuitry according to claim 9 , wherein

the driving circuit increases the driving current of the first switching element in a step-like manner at least once in reducing the driving current in a step-like manner in the second period.

12 . The electronic circuitry according to claim 9 , wherein

the driving circuit reduces the driving current of the first switching element in a ramp-like manner in the second period and sets the driving current to a fixed value at the first time.

13 . The electronic circuitry according to claim 12 , wherein

a target value of the driving current is a value that causes a voltage across a parasitic inductance of wiring at the first time to be reduced by a predetermined percentage in comparison with a case where the driving current is not reduced, the wiring connecting the first switching element and the second switching element.

14 . The electronic circuitry according to claim 13 , wherein

the driving circuit increases the driving current in a ramp-like manner after the first time and then, sets the driving current to a fixed value.

15 . The electronic circuitry according to claim 12 , wherein

the driving circuit reduces the driving current of the first switching element in a ramp-like manner over a plurality of times in the second period.

16 . The electronic circuitry according to claim 12 , wherein

the driving circuit increases the driving current of the first switching element in a ramp-like manner at least once in reducing the driving current in a ramp-like manner in the second period.

17 . An electronic system, comprising:

the electronic circuitry according to claim 9 ; and

a control circuit configured to provide waveform information of the driving current to the driving circuit of the electronic circuitry, wherein

the driving circuit generates the driving current based on the waveform information.

18 . The electronic system according to claim 17 , wherein

the control circuit includes:

a detection circuit configured to detect an operating state of the first switching element;

a storage device configured to store a plurality of waveform information of the driving current; and

a selection circuit configured to select one waveform information of the driving current from the storage device, based on the operating state of the first switching element, the operating state being detected by the detection circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2022
From: KAWAI, SHUSUKE
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 061064/0024 →
Priority Claims (1)
JP 2022-044591 · Mar 18, 2022 · national
Continuity (1)
Related Publication 20230299657A1 · Sep 21, 2023
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