Signal generation apparatus, signal generation method, and computer program

1 . A signal generation device comprising:

a digital signal processor;

a plurality of digital-analog converters configured to respectively convert a plurality of digital signals output from the digital signal processor into analog signals; and

an analog multiplexer configured to interleave the analog signals respectively output from the plurality of digital-analog converters to generate a broadband signal,

wherein the digital signal processor includes a serial-parallel converter configured to divide an input signal into a number according to a ratio between a sampling frequency of the plurality of digital-analog converters and a clock frequency of the analog multiplexer in a time domain to generate a plurality of divided signals,

a plurality of convolution arithmetic operators configured to perform a convolution arithmetic operation for the plurality of divided signals generated by the serial-parallel converter, and

a plurality of adders configured to add the plurality of divided signals for which the convolution arithmetic operation has been performed by the plurality of convolution arithmetic operators to generate a plurality of digital signals corresponding to the respective digital-analog converters.

2 . The signal generation device according to claim 1 , wherein,

in a case where the clock frequency for driving the analog multiplexer is ½ of a sampling frequency of the broadband signal,

the plurality of convolution arithmetic operators is four convolution arithmetic operators,

the plurality of adders is two adders,

the serial-parallel converter divides the input signal into two pieces in the time domain to generate two divided signals,

the four convolution arithmetic operators multiply one divided signal by a response function for every two convolution arithmetic operators included in the four convolution arithmetic operators, and

the two adders add the plurality of divided signals for which the convolution arithmetic operation has been performed by the four convolution arithmetic operators to generate the plurality of digital signals corresponding to the respective digital-analog converters.

3 . The signal generation device according to claim 1 , wherein,

in a case where the clock frequency for driving the analog multiplexer is ¼ of a sampling frequency of the broadband signal,

the plurality of convolution arithmetic operators is sixteen convolution arithmetic operators,

the plurality of adders is four adders,

two parallel-serial converters configured to perform parallel-serial conversion for the plurality of divides output from the four adders are further included,

the serial-parallel converter divides the input signal into four pieces in the time domain to generate four divided signals,

the sixteen convolution arithmetic operators multiply one divided signal by a response function for every a four convolution arithmetic operators included in the four convolution arithmetic operators,

the four adders add the plurality of divided signals for which the convolution arithmetic operation has been performed by the sixteen convolution arithmetic operators to generate the plurality of digital signals corresponding to the respective digital-analog converters, and

each of the two parallel-serial converters performs parallel-serial conversion for the plurality of digital signals output from two adders included the four adders that are different from each other.

4 . The signal generation device according to claim 1 , wherein,

in a case where the clock frequency for driving the analog multiplexer is ⅙ of a sampling frequency of the broadband signal,

the plurality of convolution arithmetic operators is thirty-six convolution arithmetic operators,

the plurality of adders is six adders,

two parallel-serial converters that perform parallel-serial conversion for the plurality of digital signals output from the six adders are further included,

the serial-parallel converter divides the input signal into six pieces in the time domain to generate six divided signals,

the thirty-six convolution arithmetic operators multiply one divided signal by a response function for every six convolution arithmetic operators included in the thirty-six convolution arithmetic operators,

the six adders add the plurality of divided signals for which the convolution arithmetic operation has been performed by the thirty-six convolution arithmetic operators to generate the plurality of digital signals corresponding to the respective digital-analog converters, and

each of the two parallel-serial converters performs parallel-serial conversion for the plurality of digital signals output from three adders included in the six adders that are different from one another.

5 . A signal generation method comprising:

by a digital signal processor, dividing an input signal into a number according to a ratio between a sampling frequency of a plurality of digital-analog converters and a clock frequency of an analog multiplexer in a time domain to generate a plurality of divided signals;

by the digital signal processor, performing a convolution arithmetic operation for the plurality of divided signals;

by the digital signal processor, adding the plurality of divided signals for which the convolution arithmetic operation has been performed to generate a plurality of digital signals corresponding to the respective digital-analog converters;

by the plurality of digital-analog converters, respectively converting the plurality of digital signals output from the digital signal processor into analog signals; and

by the analog multiplexer, interleaving the analog signals respectively output from the plurality of digital-analog converters to generate a broadband signal.

6 . A non-transitory storage medium that stores a program for making a computer perform processes, the processes comprising:

dividing an input signal into a number according to a ratio between a sampling frequency of a plurality of digital-analog converters and a clock frequency of an analog multiplexer in a time domain to generate a plurality of divided signals;

performing a convolution arithmetic operation for the plurality of divided signals;

adding the plurality of divided signals for which the convolution arithmetic operation has been performed to generate a plurality of digital signals corresponding to the respective digital-analog converters;

converting the plurality of digital signals into analog signals; and

interleaving the analog signals to generate a broadband signal.