Semiconductor devices
A semiconductor device may include a substrate including an active pattern, a conductive filling pattern on an impurity region at an upper portion of the active pattern, a first spacer and a second spacer stacked on a sidewall of the conductive filling pattern in a horizontal direction, and a bit line structure on the conductive filling pattern. The impurity region may include impurities. The horizontal direction may be parallel to an upper surface of the substrate. The first spacer may include an insulating material containing the impurities.
1 . A semiconductor device comprising:
a substrate including an active pattern, the active pattern including an impurity region at an upper portion of the active pattern, the impurity region including impurities;
a conductive filling pattern on the impurity region;
a first spacer and a second spacer stacked on a sidewall of the conductive filling pattern in a horizontal direction, the horizontal direction being parallel to an upper surface of the substrate; and
a bit line structure on the conductive filling pattern,
wherein the first spacer includes an insulating material containing the impurities.
2 . The semiconductor device according to claim 1 , wherein
the impurity region includes silicon doped with phosphorous, and
the first spacer includes phosphorous silicate glass (PSG).
3 . The semiconductor device according to claim 1 , wherein the second spacer includes a low-k dielectric material or silicon nitride.
4 . The semiconductor device according to claim 1 , further comprising:
an ohmic contact pattern, wherein
the conductive filling pattern includes a metal,
the ohmic contact pattern is between the impurity region and the conductive filling pattern, and
the ohmic contact pattern includes a metal silicide.
5 . The semiconductor device according to claim 4 , wherein
the conductive filling pattern includes a first conductive pattern and a second conductive pattern,
the second conductive pattern includes a metal or a metal nitride,
the first conductive pattern covers a sidewall of the second conductive pattern, and
the first conductive pattern includes a metal.
6 . The semiconductor device according to claim 5 , wherein the ohmic contact pattern includes a silicide of the metal included in the first conductive pattern.
7 . The semiconductor device according to claim 1 , wherein
the impurity region is in an upper portion of a central portion of the active pattern, and
an upper surface of the impurity region is lower than upper surfaces of opposite end portions of the active pattern.
8 . The semiconductor device according to claim 7 , further comprising:
an isolation pattern on a sidewall of the active pattern;
a conductive pad structure on the active pattern and the isolation pattern, wherein
the conductive pad structure overlaps at least a portion of the conductive filling pattern in a horizontal direction, and
the horizontal direction is parallel to the upper surface of the substrate.
9 . The semiconductor device according to claim 8 , further comprising:
a contact plug structure on the conductive pad structure; and
a capacitor on the contact plug structure, wherein
the conductive pad structure contacts the opposite end portions of the active pattern.
10 . The semiconductor device according to claim 1 , wherein
the conductive filling pattern includes a lower portion and an upper portion contacting each other, and
a width of the lower portion of the conductive filling pattern is greater than a width of the upper portion of the conductive filling pattern.
11 . A semiconductor device comprising:
a substrate including an active pattern protruding in a vertical direction from an upper surface of the substrate, the vertical direction being perpendicular to the upper surface of the substrate;
an isolation pattern covering a sidewall of the active pattern;
a conductive filling pattern on the active pattern, an impurity region at a portion of the active pattern being under the conductive filling pattern, the conductive filling pattern including a metal, the impurity region including n-type impurities;
a spacer structure on a sidewall of the conductive filling pattern, the spacer structure including an insulating material containing the n-type impurities; and
a bit line structure on the conductive filling pattern.
12 . The semiconductor device according to claim 11 , wherein
the spacer structure includes phosphorous silicate glass (PSG), and
the impurity region includes silicon doped with phosphorous.
13 . The semiconductor device according to claim 11 , wherein
the spacer structure includes a first spacer and a second spacer,
the first spacer is on an outer sidewall of the second spacer,
the first spacer includes the n-type impurities, and
the second spacer covers the sidewall of the conductive filling pattern.
14 . The semiconductor device according to claim 13 , wherein the second spacer includes a low-k dielectric material or silicon nitride.
15 . The semiconductor device according to claim 11 , further comprising:
an ohmic contact pattern between the impurity region and the conductive filling pattern, wherein
the ohmic contact pattern includes a metal silicide.
16 . The semiconductor device according to claim 15 , wherein
the conductive filling pattern includes a first conductive pattern and a second conductive pattern,
the first conductive pattern covers a sidewall of the second conductive pattern,
the first conductive pattern includes a metal, and
the second conductive pattern includes a metal or a metal nitride.
17 . The semiconductor device according to claim 16 , wherein the ohmic contact pattern includes a silicide of the metal included in the first conductive pattern.
18 . A semiconductor device comprising:
a substrate including an active pattern protruding in a vertical direction from an upper surface of a substrate, the vertical direction being perpendicular to the upper surface of the substrate;
an isolation pattern covering a sidewall of the active pattern;
an ohmic contact pattern on a central portion of the active pattern, an impurity region at a portion of the active pattern being under the ohmic contact pattern, the impurity region including n-type impurities;
a conductive filling pattern on the ohmic contact pattern;
a spacer structure on a sidewall of the conductive filling pattern;
a bit line structure on the conductive filling pattern;
a conductive pad structure on each of opposite end portions of the active pattern, the conductive pad structure overlapping at least a portion of the conductive filling pattern in a horizontal direction, the horizontal direction being parallel to the upper surface of the substrate;
a contact plug structure on the conductive pad structure; and
a capacitor on the conductive pad structure,
wherein the spacer structure includes an insulating material containing the n-type impurities.
19 . The semiconductor device according to claim 18 , wherein
the impurity region includes silicon doped with phosphorous, and
the spacer structure includes phosphorous silicate glass (PSG).
20 . The semiconductor device according to claim 18 , wherein
the spacer structure includes a first spacer and a second spacer,
the first spacer is on an outer sidewall of the second spacer,
the first spacer includes the n-type impurities, and
the second spacer covers the sidewall of the conductive filling pattern.