Semiconductor devices
A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.
1 . A semiconductor device, comprising:
a substrate including a cell active region, a first peripheral active region, a second peripheral active region, and an isolation structure between the first peripheral active region and the second peripheral active region;
a first gate structure arranged on the first peripheral active region of the substrate and including a first high-k dielectric pattern and a first metal pattern;
a channel layer arranged on the second peripheral active region of the substrate and including silicon germanium (SiGe); and
a second gate structure arranged on the channel layer and including a second high-k dielectric pattern, a second metal pattern and a third metal pattern on the second metal pattern,
wherein the first high-k dielectric pattern of the first gate structure includes hafnium oxide (HfO) and lanthanum oxide (LaO),
wherein the first metal pattern of the first gate structure includes titanium nitride (TiN),
wherein the second high-k dielectric pattern of the second gate structure includes hafnium oxide (HfO),
wherein the second metal pattern of the second gate structure includes titanium nitride (TiN) and aluminum oxide (AlO), and
wherein the third metal pattern of the second gate structure includes titanium nitride (TiN) and lanthanum oxide (LaO).
2 . The semiconductor device as claimed in claim 1 , wherein:
the isolation structure of the substrate includes an inner wall oxide pattern, a liner on the inner wall oxide pattern, and a filling insulation pattern on the liner, and
a thickness of the inner wall oxide pattern of the isolation structure of the substrate is greater than a thickness of the liner of the isolation structure of the substrate.
3 . The semiconductor device as claimed in claim 1 , wherein:
the isolation structure of the substrate includes an inner wall oxide pattern, a liner on the inner wall oxide pattern, and a filling insulation pattern on the liner, and
a top surface of the liner of the isolation structure of the substrate is higher than a top surface of the inner wall oxide pattern of the isolation structure of the substrate and a top surface of the filling insulation pattern of the isolation structure of the substrate.
4 . The semiconductor device as claimed in claim 1 , wherein:
the first gate structure includes a first interface insulation pattern that is between the first peripheral active region of the substrate and the first high-k dielectric pattern of the first gate structure, and
the first interface insulation pattern of the first gate structure includes silicon oxide and/or silicon oxynitride.
5 . The semiconductor device as claimed in claim 1 , wherein:
the second gate structure includes a second interface insulation pattern that is between the second peripheral active region of the substrate and the second high-k dielectric pattern of the second gate structure, and
the second interface insulation pattern of the second gate structure includes silicon oxide and/or silicon oxynitride.
6 . The semiconductor device as claimed in claim 1 , wherein:
the isolation structure of the substrate includes an inner wall oxide pattern, a liner on the inner wall oxide pattern, and a filling insulation pattern on the liner,
each of the inner wall oxide pattern and the filling insulation pattern of the isolation structure of the substrate includes silicon oxide, and
the liner of the isolation structure of the substrate includes silicon nitride.
7 . The semiconductor device as claimed in claim 1 , wherein:
each of the first gate structure and the second gate structure includes a polysilicon pattern, a fourth metal pattern, and a capping pattern, and
the fourth metal pattern of each of the first gate structure and the second gate structure includes titanium nitride (TiN) and tungsten (W).
8 . A semiconductor device, comprising:
a substrate including a cell active region, a first peripheral active region, a second peripheral active region, and an isolation structure between the first peripheral active region and the second peripheral active region;
a first gate structure arranged on the first peripheral active region of the substrate and including a first high-k dielectric pattern and a first metal pattern;
a channel layer arranged on the second peripheral active region of the substrate and including silicon germanium (SiGe); and
a second gate structure arranged on the channel layer and including a second high-k dielectric pattern and a second metal pattern,
wherein the first high-k dielectric pattern of the first gate structure includes an oxide including hafnium (Hf), silicon (Si) and lanthanum (La),
wherein the first metal pattern of the first gate structure includes titanium nitride (TiN),
wherein the second high-k dielectric pattern of the second gate structure includes an oxide including hafnium (Hf), silicon (Si) and aluminum (Al), and
wherein the second metal pattern of the second gate structure includes titanium nitride (TiN) and lanthanum oxide (LaO).
9 . The semiconductor device as claimed in claim 8 , wherein:
the isolation structure of the substrate includes an inner wall oxide pattern, a liner on the inner wall oxide pattern, and a filling insulation pattern on the liner, and
a thickness of the inner wall oxide pattern of the isolation structure of the substrate is greater than a thickness of the liner of the isolation structure of the substrate.
10 . The semiconductor device as claimed in claim 8 , wherein:
the isolation structure of the substrate includes an inner wall oxide pattern, a liner on the inner wall oxide pattern, and a filling insulation pattern on the liner, and
a top surface of the liner of the isolation structure of the substrate is higher than a top surface of the inner wall oxide pattern of the isolation structure of the substrate and a top surface of the filling insulation pattern of the isolation structure of the substrate.
11 . The semiconductor device as claimed in claim 8 , wherein:
the first gate structure includes a first interface insulation pattern that is between the first peripheral active region of the substrate and the first high-k dielectric pattern of the first gate structure, and
the first interface insulation pattern of the first gate structure includes silicon oxide and/or silicon oxynitride.
12 . The semiconductor device as claimed in claim 8 , wherein:
the second gate structure includes a second interface insulation pattern that is between the second peripheral active region of the substrate and the second high-k dielectric pattern of the second gate structure, and
the second interface insulation pattern of the second gate structure includes silicon oxide and/or silicon oxynitride.
13 . The semiconductor device as claimed in claim 8 , wherein:
the isolation structure of the substrate includes an inner wall oxide pattern, a liner on the inner wall oxide pattern, and a filling insulation pattern on the liner,
each of the inner wall oxide pattern and the filling insulation pattern of the isolation structure of the substrate includes silicon oxide, and
the liner of the isolation structure of the substrate includes silicon nitride.
14 . The semiconductor device as claimed in claim 8 , wherein:
each of the first gate structure and the second gate structure includes a polysilicon pattern, a third metal pattern, and a capping pattern, and
the third metal pattern of each of the first gate structure and the second gate structure includes titanium nitride (TiN) and tungsten (W).
15 . A semiconductor device, comprising:
a substrate including a cell active region, a first peripheral active region, a second peripheral active region, and an isolation structure between the first peripheral active region and the second peripheral active region;
a first gate structure arranged on the first peripheral active region of the substrate and including a first high-k dielectric pattern and a n-type metal pattern;
a channel layer arranged on the second peripheral active region of the substrate and including silicon germanium (SiGe); and
a second gate structure arranged on the channel layer and including a second high-k dielectric pattern, a p-type metal pattern and a n-type metal pattern on the p-type metal pattern,
wherein the first high-k dielectric pattern of the first gate structure includes hafnium oxide (HfO) and lanthanum oxide (LaO),
wherein the second high-k dielectric pattern of the second gate structure includes hafnium oxide (HfO),
wherein the isolation structure of the substrate includes an inner wall oxide pattern, a liner on the inner wall oxide pattern, and a filling insulation pattern on the liner,
wherein a thickness of the inner wall oxide pattern of the isolation structure of the substrate is greater than a thickness of the liner of the isolation structure of the substrate,
wherein a top surface of the liner of the isolation structure of the substrate is higher than a top surface of the inner wall oxide pattern of the isolation structure of the substrate and a top surface of the filling insulation pattern of the isolation structure of the substrate,
wherein each of the inner wall oxide pattern and the filling insulation pattern of the isolation structure of the substrate includes silicon oxide (SiO),
wherein the liner of the isolation structure of the substrate includes silicon nitride (SiN), and
wherein the n-type metal pattern of the second gate structure includes lanthanum oxide (LaO).
16 . The semiconductor device as claimed in claim 15 , wherein the p-type metal pattern of the second gate structure includes at least one of aluminum (Al), aluminum oxide (AlO), titanium nitride (TiN), tungsten nitride (WN), and ruthenium oxide (RuO).
17 . The semiconductor device as claimed in claim 15 , wherein:
the first gate structure includes a first interface insulation pattern that is between the first peripheral active region of the substrate and the first high-k dielectric pattern of the first gate structure, and
the first interface insulation pattern of the first gate structure includes silicon oxide and/or silicon oxynitride.
18 . The semiconductor device as claimed in claim 15 , wherein:
the second gate structure includes a second interface insulation pattern that is between the second peripheral active region of the substrate and the second high-k dielectric pattern of the second gate structure, and
the second interface insulation pattern of the second gate structure includes silicon oxide and/or silicon oxynitride.
19 . The semiconductor device as claimed in claim 15 , wherein:
each of the first gate structure and the second gate structure includes a polysilicon pattern, a gate metal pattern, and a capping pattern, and
the gate metal pattern of each of the first gate structure and the second gate structure includes titanium nitride (TiN) and tungsten (W).