Display substrate and display device
A display substrate and a display device are provided. The display substrate includes a plurality of pads, an insulating layer and an inorganic layer located in a peripheral region. At least one of the pads includes a first conductor portion, a second conductor portion and a third conductor portion. The third conductor portion is located on a side of the second conductor portion away from abase substrate and electrically connected to the second conductor portion. The third conductor portion is electrically connected to the second conductor portion through a second via hole disposed in the inorganic layer of the peripheral region. A projection of the first conductor portion on the base substrate is located within a projection of the second via hole on the base substrate.
1 . A display substrate, comprising:
a base substrate comprising a display region and a peripheral region surrounding the display region;
a plurality of sub-pixels located in the display region and arranged in an array;
a plurality of pads located in the peripheral region, wherein at least one of the plurality of pads comprises a first conductor portion, a second conductor portion and a third conductor portion, the first conductor portion is located on the base substrate, the second conductor portion is located on a side of the first conductor portion away from the base substrate and electrically connected to the first conductor portion, and the third conductor portion is located on a side of the second conductor portion away from the base substrate and electrically connected to the second conductor portion;
an insulating layer of the peripheral region, wherein the insulating layer of the peripheral region is located in the peripheral region, and the second conductor portion is electrically connected to the first conductor portion through a first via hole disposed in the insulating layer of the peripheral region; and
an inorganic layer of the peripheral region, wherein the inorganic layer of the peripheral region is located in the peripheral region, the third conductor portion is electrically connected to the second conductor portion through a second via hole disposed in the inorganic layer of the peripheral region, and a projection of the first conductor portion on the base substrate is located within a projection of the second via hole on the base substrate;
wherein the plurality of pads comprises:
a plurality of input pads arranged along a first direction in the peripheral region on a first side of the display region, wherein the first direction is a row direction of the array of the plurality of sub-pixels; and
a plurality of output pads located between the plurality of input pads and the display region and arranged along the first direction.
2 . The display substrate according to claim 1 , further comprising:
a planarization layer of the peripheral region, wherein the planarization layer of the peripheral region is located on a side of the inorganic layer of the peripheral region facing the base substrate, and the inorganic layer of the peripheral region is in contact with the second conductor portion through a third via hole disposed in the planarization layer of the peripheral region.
3 . The display substrate according to claim 1 , further comprising:
a plurality of connection pads located in the peripheral region, wherein on a side of the plurality of input pads away from the display region, the first conductor portion of the input pad is electrically connected to the connection pad through a first lead disposed in the peripheral region; and
a gate driving circuit located in a peripheral region on at least a second side of the display region, wherein the gate driving circuit is connected to the plurality of sub-pixels and configured to provide a gate driving signal to the plurality of sub-pixels, wherein the first conductor portion of the output pad is electrically connected to the gate driving circuit or at least one of the plurality of sub-pixels through a second lead disposed in the peripheral region.
4 . The display substrate according to claim 3 , wherein the connection pad comprises:
a fourth conductor portion located on the base substrate and disposed in the same layer as the second conductor portion;
a fifth conductor portion located on a side of the fourth conductor portion away from the base substrate and disposed in the same layer as the third conductor portion, wherein the fifth conductor portion is electrically connected to the fourth conductor portion through a fourth via hole disposed in the inorganic layer of the peripheral region; and
a pad insulating portion located on a side of the inorganic layer of the peripheral region facing the base substrate, wherein the pad insulating portion covers an edge of the fourth conductor portion.
5 . The display substrate according to claim 4 , further comprising a planarization layer of the peripheral region, wherein the inorganic layer of the peripheral region is in contact with the fourth conductor portion through a fifth via hole disposed in the planarization layer of the peripheral region, and the pad insulating portion is disposed in the same layer as the planarization layer of the peripheral region.
6 . The display substrate according to claim 1 , wherein an edge of the projection of the first conductor portion on the base substrate is spaced from an edge of the projection of the second via hole on the base substrate by a distance of 1 μm to 2 μm.
7 . The display substrate according to claim 6 , wherein a geometric center of the projection of the first conductor portion on the base substrate substantially coincides with a geometric center of the projection of the second via hole on the base substrate, a size of the projection of the first conductor portion on the base substrate in a first direction is in a range of 12 μm to 14 μm, a size of the projection of the second via hole on the base substrate in the first direction is in a range of 14 μm to 16 μm, and the first direction is a row direction of the array of the plurality of sub-pixels.
8 . The display substrate according to claim 2 , wherein a size of a projection of the third via hole on the base substrate in a first direction is in a range of 16 μm to 20 μm.
9 . The display substrate according to claim 1 , wherein a size of a projection of the first via hole on the base substrate in a first direction is in a range of 7 μm to 9 μm.
10 . The display substrate according to claim 1 , wherein:
a sidewall of the second via hole in the inorganic layer of the peripheral region has a slope angle θ 1 with respect to a plane where the base substrate is located; and
an edge of the first conductor portion has a first surface facing the base substrate, a second surface away from the base substrate and a third surface connecting the first surface to the second surface, and the third surface of the first conductor portion has a slope angle θ 2 with respect to the plane where the base substrate is located;
wherein θ 2 <θ 1 .
11 . The display substrate according to claim 10 , wherein the slope angle θ 1 is in a range of 80° to 90°, and the slope angle θ 2 is in a range of 20° to 30°.
12 . The display substrate according to claim 1 , wherein an edge of the second conductor portion has a first surface facing the base substrate, a second surface away from the base substrate and a third surface connecting the first surface to the second surface, and the third surface of the second conductor portion has a slope angle θ 3 with respect to a plane where the base substrate is located;
wherein an edge of the third conductor portion has a first surface facing the base substrate, a second surface away from the base substrate and a third surface connecting the first surface to the second surface, and the third surface of the third conductor portion has a slope angle θ 4 with respect to the plane where the base substrate is located;
wherein a sidewall of the first via hole in the insulating layer of the peripheral region has a slope angle θ 5 with respect to the plane where the base substrate is located; and
wherein θ 5 <θ 3 <θ 4 .
13 . The display substrate according to claim 12 , wherein the slope angle θ 3 is in a range of 55° to 65°, the slope angle 04 is in a range of 58° to 67°, and the slope angle θ 5 is in a range of 40° to 50°.
14 . The display substrate according to claim 1 , wherein at least one of the plurality of sub-pixels comprises a thin film transistor having a gate electrode, a source electrode and a drain electrode, the first conductor portions of the plurality of pads are disposed in the same layer as the gate electrode, and the second conductor portions of the plurality of pads are disposed in the same layer as the source electrode and the drain electrode.
15 . The display substrate according to claim 14 , further comprising: a light-emitting element, an encapsulation layer, a first touch electrode layer, a second touch electrode layer and a touch insulating layer that are located in the display region, wherein the light-emitting element is located on a side of the thin film transistor away from the base substrate, the encapsulation layer is located on a side of the light-emitting element away from the base substrate, the first touch electrode layer is located on a side of the encapsulation layer away from the base substrate, the touch insulating layer is located on a side of the first touch electrode layer away from the base substrate and covers the first touch electrode layer, and the second touch electrode layer is located on a side of the touch insulating layer away from the base substrate;
wherein the inorganic layer of the peripheral region is disposed in the same layer as the touch insulating layer, and the third conductor portion is disposed in the same layer as at least one of the first touch electrode layer or the second touch electrode layer.
16 . The display substrate according to claim 14 , wherein the at least one of the plurality of sub-pixels further comprises an interlayer insulating layer of the display region, a first gate insulating layer of the display region and a second gate insulating layer of the display region, the interlayer insulating layer of the display region is located between the gate electrode and the source electrode and drain electrode, the first gate insulating layer of the display region is located on a side of the interlayer insulating layer of the display region facing the base substrate, and the second gate insulating layer of the display region is located between the interlayer insulating layer of the display region and the first gate insulating layer of the display region; and
wherein the insulating layer of the peripheral region comprises an interlayer insulating layer of the peripheral region and a second gate insulating layer of the peripheral region, the interlayer insulating layer of the peripheral region is disposed in the same layer as the interlayer insulating layer of the display region, and the second gate insulating layer of the peripheral region is disposed in the same layer as the second gate insulating layer of the display region.
17 . The display substrate according to claim 1 , wherein at least one of the plurality of sub-pixels comprises a thin film transistor and a transfer electrode, the thin film transistor comprises a gate electrode, a source electrode and a drain electrode, the transfer electrode is electrically connected to one of the source electrode and the drain electrode, and the second conductor portion is disposed in the same layer as at least one of the source electrode and drain electrode and the transfer electrode.
18 . A display device, comprising the display substrate according to claim 1 .