Semiconductor package and method of manufacturing the same
A semiconductor package includes a redistribution portion including an insulating layer, a redistribution layer, and a redistribution via, an under-bump metallurgy (UBM) layer below the redistribution portion and including a UBM pad on a lower surface of the redistribution portion and a UBM via on the UBM pad to penetrate through the insulating layer, a semiconductor chip on an upper surface of the redistribution portion and electrically connected to the redistribution layer, an adhesive layer between the UBM layer and the insulating layer and including a conductive material, and a connection bump below the UBM pad and connected to the UBM layer. The UBM pad has a first diameter, and the UBM via has a second diameter, less than the first diameter, and an upper surface of the UBM pad is located on the same level as, or a level lower than, a lower surface of the insulating layer.
1 . A semiconductor package comprising:
a redistribution portion including an insulating layer, a redistribution layer on the insulating layer, and a redistribution via connected to the redistribution layer;
an under-bump metallurgy (UBM) layer, the UBM layer including a UBM pad on a lower surface of the redistribution portion and a UBM via on the UBM pad, the UBM via penetrating the insulating layer;
a semiconductor chip on an upper surface of the redistribution portion and electrically connected to the redistribution layer, the upper surface of the redistribution portion being opposite to the lower surface of the redistribution portion;
an adhesive layer between the UBM layer and the insulating layer, the adhesive layer including a conductive material; and
a connection bump below the UBM pad and connected to the UBM layer,
wherein:
the UBM pad has a first diameter, and the UBM via has a second diameter less than the first diameter,
an upper surface of the UBM pad is at a same level as, or at a level lower than, a lower surface of the insulating layer,
the redistribution via is between the redistribution layer and the UBM layer,
the UBM via has an upper surface and a lower surface opposite to the upper surface of the UBM via,
the UBM via is between the UBM pad and the redistribution via such that the upper surface of the UBM via faces a lower surface of the redistribution via,
the UBM pad has an upper surface and a lower surface opposite to the upper surface of the UBM pad, the upper surface of the UBM pad facing the lower surface of the UBM via,
a sidewall of the redistribution via has a first taper such that a width of the redistribution via increases with distance away from the lower surface of the redistribution via and towards the redistribution layer,
a sidewall of the UBM via has a second taper such that a width of the UBM via increases with distance away from the upper surface of the UBM via and towards the UBM pad, and
a sidewall of the UBM pad has a third taper such that a width of the UBM pad increases with distance away from the lower surface of the UBM pad and towards the UBM via.
2 . The semiconductor package of claim 1 , wherein the UBM via is buried in the insulating layer and protrudes downwardly from the lower surface of the insulating layer by a thickness of the adhesive layer.
3 . The semiconductor package of claim 1 , wherein the sidewall of the UBM pad and the sidewall of the UBM via have different inclinations.
4 . The semiconductor package of claim 3 , wherein, when viewed in cross-section,
a width of an upper end of the UBM pad is greater than a width of a lower end of the UBM pad.
5 . The semiconductor package of claim 1 , wherein a crystal structure of the UBM pad and the UBM via is different from a crystal structure of the redistribution layer and the redistribution via.
6 . The semiconductor package of claim 5 , wherein:
the crystal structure of the UBM pad and the UBM via has a pancaked grain structure, and
the crystal structure of the redistribution layer and the redistribution via has a columnar grain structure.
7 . The semiconductor package of claim 1 , wherein a thickness of the UBM pad is in a range of about 2 μm to about 12 μm.
8 . The semiconductor package of claim 1 , wherein the UBM pad and the UBM via are an integrated body.
9 . The semiconductor package of claim 1 , wherein the adhesive layer extends along the upper surface of the UBM pad, the sidewall of the UBM via, and the upper surface of the UBM via.
10 . The semiconductor package of claim 1 , wherein the conductive material of the adhesive layer includes a material different from a material of the UBM via and a material of the redistribution via.
11 . The semiconductor package of claim 1 , wherein the connection bump covers the lower surface and at least a portion of the sidewall of the UBM pad.
12 . The semiconductor package of claim 1 , wherein the redistribution layer and the redistribution via include a plating seed layer, the plating seed layer extending along a lower surface of the redistribution layer, the sidewall of the redistribution via, and the lower surface of the redistribution via.
13 . The semiconductor package of claim 1 , wherein a portion of the redistribution portion does not overlap the semiconductor chip when viewed in a plan view.
14 . A semiconductor package comprising:
a redistribution portion including an insulating layer, a redistribution layer on the insulating layer, a redistribution via connected to the redistribution layer, and a seed layer between the insulating layer and the redistribution layer and covering a side surface and a lower surface of the redistribution via such that the seed layer is between the insulating layer and the redistribution via;
an under-bump metallurgy (UBM) layer below a lower surface of the redistribution portion and electrically connected to the redistribution layer through the redistribution via;
a semiconductor chip on an upper surface of the redistribution portion and electrically connected to the redistribution layer;
an adhesive layer on the lower surface of the redistribution portion and between the redistribution portion and the UBM layer; and
a connection bump below the UBM layer and connected to the UBM layer,
wherein:
a crystal structure of the UBM layer and a crystal structure of the redistribution layer are different, and
a portion of the adhesive layer on an uppermost surface of the UBM layer is in contact with the insulating layer.
15 . The semiconductor package of claim 14 , wherein:
the crystal structure of the UBM layer has a pancaked grain structure, and
the crystal structure of the redistribution layer and a crystal structure of the redistribution via have a columnar grain structure.
16 . The semiconductor package of claim 14 , wherein, in the UBM layer, an upper end has a first diameter and a lower end has a second diameter less than the first diameter.
17 . The semiconductor package of claim 14 , wherein an entirety of the UBM layer is on the lower surface of the redistribution portion.
18 . The semiconductor package of claim 14 , wherein:
the UBM layer includes a UBM pad on the lower surface of the redistribution portion, and a UBM via in the insulating layer and on the UBM pad, and
when viewed in cross-section, a diameter of the UBM pad increases upwardly, and a diameter of the UBM via decreases upwardly.
19 . A semiconductor package comprising:
a redistribution portion including an insulating layer and a redistribution structure on the insulating layer, the redistribution structure including a redistribution via;
an under-bump metallurgy (UBM) layer below the redistribution portion, the UBM layer including
a UBM pad below a lower surface of the redistribution portion and
a UBM via in the insulating layer, on the UBM pad, and connecting the redistribution structure and the UBM pad;
a semiconductor chip on an upper surface of the redistribution portion and electrically connected to the redistribution structure, the upper surface of the redistribution portion being opposite to the lower surface of the redistribution portion; and
a connection bump below the UBM pad and connected to the UBM pad,
wherein:
the UBM via has an upper surface and a lower surface opposite to the upper surface of the UBM via,
the UBM via is between the UBM pad and the redistribution via such that the upper surface of the UBM via faces a lower surface of the redistribution via,
the UBM pad has an upper surface and a lower surface opposite to the upper surface of the UBM pad, the upper surface of the UBM pad facing the lower surface of the UBM via,
when viewed in cross-section, the upper surface of the UBM pad has a first width as a distance between sidewalls of the UBM pad, the lower surface of the UBM pad has a second width as the distance between the sidewalls of the UBM pad, and the second width is less than the first width,
when viewed in the cross-section, the upper surface of the UBM via has a third width as a distance between sidewalls of the UBM via, the lower surface of the UBM via has a fourth width as the distance between the sidewalls of the UBM via, and the fourth width is greater than the third width,
when viewed in the cross-section, an upper surface of the redistribution via has a fifth width as a distance between sidewalls of the redistribution via, the lower surface of the redistribution via has a sixth width as the distance between the sidewalls of the redistribution via, and the sixth width is less than the fifth width, and
the sixth width is less than the third width.
20 . The semiconductor package of claim 19 , wherein the first width is greater than the fourth width.