IP Library › Granted Patent US 12,631,911
Granted Patent B2
US 12,631,911 · App. 18/297,321 · Granted May 19, 2026

Integration of advanced photonic materials in silicon photonic platform

Inventors: Vipulkumar K. Patel (Breinigsville, PA); Ming Gai Stanley Lo (Breinigsville, PA); Mark A. Webster (Bethlehem, PA); Farnood Khalilzadeh Rezaie (Irvine, CA)
Assignee: Cisco Technology, Inc.
G02F1/035G02B6/12002G02B6/12004G02F1/025G02F2202/20
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Quick Facts
Patent No.
US 12,631,911
App. No.
18/297,321
Granted
May 19, 2026
Kind
B2
Abstract

Embodiments herein describe a photonic platform having a chiplet with a Pockels effect electro-optic layer made of LN or BTO and a substrate. The chiplet is bonded to a photonic wafer which includes a waveguide. In this manner, a ridge waveguide formed by the Pockels effect electro-optic layer and the waveguide utilizes electro-optic effects to tune a signal.

Claims (37)

1 . A method of manufacturing a photonic platform, comprising:

providing a chiplet comprising:

a Pockels effect electro-optic layer, and

a substrate,

the method further comprising:

bonding the chiplet to a photonic wafer such that the Pockels effect electro-optic layer is optically coupled to a waveguide disposed within the photonic wafer;

forming a first electrode to form an electrical connection with a first insulator layer distal from a midline of the chiplet or with the Pockels effect electro-optic layer;

forming a metal routing layer, comprising:

a first metal connection electrically coupled to the first electrode, wherein the first electrode is arranged between the metal routing layer and the electro-optic layer;

forming a second electrode, the second electrode extending from the photonic wafer to the first metal connection; and

removing the substrate after bonding the chiplet to the photonic wafer.

2 . The method of claim 1 , wherein the Pockels effect electro-optic layer comprises one of BTO or LN.

3 . The method of claim 2 , wherein the Pockels effect electro-optic layer does not include silicon.

4 . The method of claim 1 , further comprising forming a third electrode to form an electrical connection with the first insulator layer of the chiplet distal from both the first electrode and the midline of the chiplet, wherein the first and third electrodes are controlled to generate an electric field in the Pockels effect electro-optic layer and the waveguide.

5 . The method of claim 4 , wherein forming the first and third electrodes is part of a back end of line (BEOL) process.

6 . The method of claim 5 , wherein forming the metal routing layer is part of the BEOL process.

7 . The method of claim 1 , further comprising:

performing a front end of line (FEOL) process to form the waveguide in the photonic wafer, wherein bonding the chiplet is part of a Middle End of Line (MEOL) process.

8 . The method of claim 7 further comprising, adding a second waveguide between the waveguide and a substrate of the photonic wafer.

9 . The method of claim 7 further comprising: bonding a laser structure to a same surface of the photonic wafer as the chiplet is bonded to.

10 . A silicon photonic platform comprising:

a semiconductor wafer comprising a waveguide;

a Pockels effect electro-optic layer disposed over, and optically coupled to, the waveguide;

a first electrode electrically coupled to a first end of the Pockels effect electro-optic layer;

a second electrode electrically coupled to a second end of the Pockels effect electro-optic layer wherein a wafer bondline is disposed between the Pockels effect electro-optic layer and the waveguide;

a first metal routing layer, comprising:

a first metal connection electrically coupled to the first electrode, wherein the first electrode is arranged between the first metal routing layer and the electro-optic layer; and

a third electrode extending from the semiconductor wafer to the first metal connection.

11 . The silicon photonic platform of claim 10 , wherein the Pockels effect electro-optic layer is bonded to the semiconductor wafer as a Middle End of Line (MEOL) process.

12 . The silicon photonic platform of claim 10 , wherein the Pockels effect electro-optic layer and the waveguide form a ridge waveguide.

13 . The silicon photonic platform of claim 12 , wherein a second waveguide is disposed within the semiconductor wafer between the waveguide and a substrate of the semiconductor wafer.

14 . The silicon photonic platform of claim 12 , wherein the Pockels effect electro-optic layer comprises one of BTO or LN.

15 . The silicon photonic platform of claim 14 , wherein the Pockels effect electro-optic layer does not include any silicon.

16 . The silicon photonic platform of claim 15 , further comprising a laser structure in a same layer as the Pockels effect electro-optic layer.

17 . The silicon photonic platform of claim 15 , wherein the Pockels effect electro-optic layer is disposed between the first metal routing layer and the waveguide.

18 . The silicon photonic platform of claim 17 , further comprising a through silicon via connecting the first metal routing layer to a substrate of the semiconductor wafer.

19 . The silicon photonic platform of claim 17 , further comprising a second metal routing layer connected to the first metal routing layer, wherein the first and second metal routing layers are formed in a Back End of Line (BEOL) processes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2023
From: PATEL, VIPULKUMAR K.; LO, MING GAI STANLEY; WEBSTER, MARK A.; KHALILZADEH REZAIE, FARNOOD
To: CISCO TECHNOLOGY, INC.
Reel/Frame 063261/0115 →
Continuity (1)
Related Publication 20240337870A1 · Oct 10, 2024
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