Fused instruction operation for performing an operation and adjusting a sign of the operation result
Techniques are disclosed involving fusing instruction pairs and executing corresponding fused instruction operations. A processor includes fusion detection circuitry to detect a pair of fetched instructions and fuse the instructions into a fused instruction operation, and execution circuitry to execute the fused instruction operation. In one embodiment, a first instruction is executable to perform an operation and a second instruction is executable to adjust a sign of a result of the operation. In another embodiment, the first instruction is executable to perform an operation and the second instruction is executable to find a maximum or minimum, as compared to a comparison operand, of a result of the operation. In another embodiment, the first instruction is executable to perform a vector operation and the second instruction is executable to read a first element of the vector result and overwrite one or more additional elements of the vector result.
1 . A processor, comprising:
a hardware fetch and decode circuit including hardware pair detector circuitry, wherein the hardware pair detector circuitry is configured to:
receive fetched instructions;
detect a first instruction that is executable to perform an arithmetic/logic operation and a second instruction that is executable to adjust a sign of a result of the arithmetic/logic operation;
determine whether the first instruction and the second instruction are eligible for fusion; and
in response to determining that the first instruction and the second instruction are eligible for fusion,
generate, for a first instruction operation decoded from the first instruction, an indicator of eligibility for fusion with a second instruction operation decoded from the second instruction; and
forward from the hardware fetch and decode circuit the indicator of eligibility with the first instruction operation and the second instruction operation;
a hardware map-dispatch-rename (MDR) circuit including hardware fusion circuitry, wherein:
the hardware MDR circuit is configured to:
receive the first instruction operation and the second instruction operation;
detect the indicator of eligibility, if received; and
based in part on whether the indicator of eligibility is detected, determine whether to fuse the first instruction operation and the second instruction operation; and
the hardware fusion circuitry is configured to fuse the first instruction operation and the second instruction operation into a fused instruction operation that is executable to perform the arithmetic/logic operation and adjust the sign of the result; and
hardware execution circuitry coupled to the hardware MDR circuit and configured to execute the fused instruction operation.
2 . The processor of claim 1 , wherein the second instruction is a negation instruction, and the fused instruction operation is executable to negate the result of the arithmetic/logic operation.
3 . The processor of claim 1 , wherein the second instruction is an absolute value instruction, and the fused instruction operation is executable to take an absolute value of the result of the arithmetic/logic operation.
4 . The processor of claim 1 , wherein the hardware execution circuitry comprises:
a hardware arithmetic/logic operation execution circuit; and
a hardware sign adjust circuit.
5 . The processor of claim 4 , further comprising an additional hardware sign adjust circuit, and wherein the processor is configured to use the additional hardware sign adjust circuit to execute non-fused sign adjust instruction operations but not to execute the fused instruction operation.
6 . The processor of claim 1 , wherein:
the first instruction and the second instruction are floating-point instructions;
the fused instruction operation is a floating-point instruction operation; and
the hardware execution circuitry is floating-point hardware execution circuitry.
7 . The processor of claim 1 , wherein:
the hardware pair detector circuitry is further configured to, in response to determining that the first instruction and the second instruction are eligible for fusion,
generate for the second instruction operation an indicator of a type of operation performed by execution of the second instruction, and
forward from the hardware fetch and decode circuit the indicator of a type of operation with the second instruction operation;
the hardware pair detector circuitry is further configured to, in response to determining that the first instruction and the second instruction are not eligible for fusion, forward from the hardware fetch and decode circuit the first instruction operation and the second instruction operation without generating the indicator of eligibility or the indicator of a type of operation; and
the hardware MDR circuit is further configured to:
detect the indicator of a type of operation, if received; and
determine whether to fuse the first instruction operation and the second instruction operation based in part on the indicator of a type of operation.
8 . The processor of claim 7 , wherein the hardware fusion circuitry is further configured to associate the indicator of a type of operation with the fused instruction operation.
9 . The processor of claim 1 , wherein the indicator of eligibility for fusion is within the first instruction operation.
10 . The processor of claim 1 , wherein the hardware MDR circuit is further configured to determine whether to fuse the first instruction operation and the second instruction operation based in part on an availability of the hardware execution circuitry.
11 . A method, comprising:
detecting, by a hardware fetch and decode circuit of a processor, a first instruction that is executable by the processor to perform an arithmetic/logic operation and a second instruction that is executable by the processor to adjust a sign of a result of the arithmetic/logic operation;
decoding, by the hardware fetch and decode circuit, the first instruction and the second instruction into a first instruction operation and a second instruction operation for execution;
determining, by the hardware fetch and decode circuit, that the first instruction and the second instruction are eligible for fusion;
in response to determining that the first instruction and the second instruction are eligible for fusion, generating for the first instruction operation an indicator of eligibility for fusion with the second instruction operation;
forwarding, to a hardware map-dispatch-rename (MDR) circuit of the processor, the first instruction operation, the indicator of eligibility and the second instruction operation;
based in part on the indicator of eligibility, determining, in the hardware MDR circuit, that the first instruction operation and the second instruction operation should be fused;
in response to determining that the first instruction operation and the second instruction operation should be fused, fusing the first instruction operation and the second instruction operation into a fused instruction operation that is executable by the processor to perform the arithmetic/logic operation and adjust the sign of the result; and
executing, by the processor, the fused instruction operation.
12 . The method of claim 11 , wherein the second instruction is a negation instruction and the fused instruction operation is executable to negate the result of the arithmetic/logic operation.
13 . The method of claim 11 , wherein the second instruction is an absolute value instruction, and the fused instruction operation is executable to take an absolute value of the result of the arithmetic/logic operation.
14 . The method of claim 11 , wherein executing the fused instruction operation comprises using an arithmetic/logic operation execution circuit dedicated to execution of fused instruction operations in lieu of an additional arithmetic/logic operation execution circuit used for execution of non-fused instruction operations.
15 . The method of claim 11 , wherein the first instruction and the second instruction are floating-point instructions and the fused instruction operation is a floating point instruction operation.
16 . A system, comprising:
one or more memory controllers;
one or more peripheral components;
a processor; and
a communication fabric configured to interconnect the one or more memory controllers, the one or more peripheral components and the processor, wherein the processor includes:
a hardware fetch and decode circuit including hardware pair detector circuitry, wherein the hardware pair detector circuitry is configured to:
receive fetched instructions;
detect a first instruction that is executable to perform an arithmetic/logic operation and a second instruction that is executable to adjust a sign of a result of the arithmetic/logic operation;
determine whether the first instruction and the second instruction are eligible for fusion; and
in response to determining that the first instruction and the second instruction are eligible for fusion,
generate, for a first instruction operation decoded from the first instruction, an indicator of eligibility for fusion with a second instruction operation decoded from the second instruction; and
forward from the hardware fetch and decode circuit the first instruction operation with the indicator of eligibility and the second instruction operation;
a hardware map-dispatch-rename (MDR) circuit including hardware fusion circuitry, wherein:
the hardware MDR circuit is configured to:
receive the first instruction operation and the second instruction operation;
detect the indicator of eligibility, if received; and
based on whether the indicator of eligibility is detected, determine whether to fuse the first instruction operation and the second instruction operation; and
the hardware fusion circuitry is configured to fuse the first instruction operation and the second instruction operation into a fused instruction operation that is executable to perform the arithmetic/logic operation and adjust the sign of the result; and
hardware execution circuitry coupled to the hardware fusion circuitry and configured to execute the fused instruction operation.
17 . The system of claim 16 , wherein the second instruction is a negation instruction, and the fused instruction operation is executable to negate the result of the arithmetic/logic operation.
18 . The system of claim 16 , wherein the second instruction is an absolute value instruction, and the fused instruction operation is executable to take an absolute value of the result of the arithmetic/logic operation.
19 . The system of claim 16 , wherein the hardware execution circuitry comprises:
a hardware arithmetic/logic operation execution circuit; and
a hardware sign adjust circuit.
20 . The system of claim 19 , wherein the processor further comprises an additional hardware sign adjust circuit, and wherein the processor is configured to use the additional hardware sign adjust circuit to execute non-fused sign adjust instruction operations but not to execute the fused instruction operation.