Self-resetting clock generator
An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1→0) ST CLK # based on PCLK assertion (0→1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.
1 . A self-resetting clock generator circuit comprising:
a keeper-free clock gate configured to generate a positive clock (PCLK) signal based on an enable (ENBL) signal, the PCLK fed back as input, a reset (RST) signal, and an external clock (SOC CLK);
a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK and a negated return clock (RETCLK #);
a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1→0) self-timed clock signal (ST CLK #) based on PCLK assertion (0→1);
a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.
2 . The circuit of claim 1 , further comprising a tracking circuit configured to control a state of a return clock (RET CLK) signal coupled to the first bank of transistors, assertion of the RET CLK signal causing the ST CLK # signal to change state.
3 . The circuit of claim 1 , wherein the circuit is configured such that a (1→0) transition of ST CLK # de-asserts PCLK.
4 . The circuit of claim 3 , wherein the transition of ST CLK # de-asserts PCLK after a configurable delay.
5 . The circuit of claim 1 , wherein the logic gate based reset circuit includes:
a first gate configured to receive the ST CLK # signal and the RST signal and generate an intermediate signal (X 0 ); and
a second gate configured to receive the X 0 signal and the SOC CLK and generate the RST signal.
6 . The circuit of claim 1 , wherein the first bank of transistors includes a plurality of drain connected transistors with gates controlled by PCLK.
7 . The circuit of claim 5 , wherein the second bank of transistors includes a second plurality of drain connected transistors with a gate of one of the transistors of the second plurality of transistors controlled by PCLK.
8 . A system comprising:
a memory device including a self-resetting clock generator circuit, the self-resetting clock generator circuit comprising:
a keeper-free clock gate configured to generate a positive clock (PCLK) signal based on an enable (ENBL) signal, a reset (RST) signal, and an external clock (SOC CLK);
a first bank of transistors configured to assert a self-timed clock signal (ST CLK #); and
a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1→0) ST CLK # based on PCLK assertion (0→1).
9 . The system of claim 8 , wherein the self-resetting clock generator includes a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.
10 . The system of claim 8 , further comprising a tracking circuit configured to control a state of a return clock (RET CLK) signal coupled to the first bank of transistors, assertion of the RET CLK signal causing the ST CLK # signal to change state.
11 . The system of claim 8 , wherein the circuit is configured such that a (1→0) transition of ST CLK # de-asserts PCLK.
12 . The system of claim 11 , wherein the transition of ST CLK # de-asserts PCLK after a configurable delay.
13 . The system of claim 8 , wherein the logic gate based reset circuit includes:
a first gate configured to receive the ST CLK # signal and the RST signal and generate an intermediate signal (X 0 ); and
a second gate configured to receive the X 0 signal and the SOC CLK and generate the RST signal.
14 . The system of claim 8 , wherein the first bank of transistors includes a plurality of drain connected transistors with gates controlled by PCLK.
15 . The system of claim 14 , wherein the second bank of transistors includes a second plurality of drain connected transistors with a gate of one of the transistors of the second plurality of transistors controlled by PCLK.
16 . A method for generating a clock signal for a memory, the method comprising:
generating, by a keeper-free clock gate, a positive clock (PCLK) signal based on an enable (ENBL) signal, a reset (RST) signal, the PCLK fed back as input, and an external clock (SOC CLK);
de-asserting self-timed clock signal (ST CLK #) based on assertion of the PCLK; and
asserting an self-timed clock signal (ST CLK) based on de-assertion of the ST CLK #.
17 . The method of claim 16 , further comprising generating, by a logic gate-based reset circuit, the RST signal based on the SOC CLK and the ST CLK #.
18 . The method of claim 16 , further comprising controlling, by a tracking circuit, a state of a return clock (RET CLK) signal coupled to a first bank of transistors, assertion of the RET CLK signal causing the ST CLK # signal to change state.
19 . The method of claim 16 , wherein the self-resetting clock generator circuit is configured such that a (1→0) transition of ST CLK # de-asserts PCLK.
20 . The method of claim 18 , wherein the transition of ST CLK # de-asserts PCLK after a configurable delay.