Three-dimensional memory device with a cutting structure and method for forming the same
A three-dimensional memory device includes memory arrays stacking in a first direction. Each of the memory arrays includes a stack structure including interleaved conductive layers and first dielectric layers extending in a second direction perpendicular to the first direction and a third direction perpendicular to the first direction and the second direction. The conductive layers include word lines and a drain select gate line, and the drain select gate line is separated by a second dielectric layer in the second direction.
1 . A three-dimensional (3D) memory device, comprising:
memory arrays stacking in a first direction, each of the memory arrays comprising:
a stack structure comprising interleaved conductive layers and first dielectric layers extending in a second direction perpendicular to the first direction and a third direction perpendicular to the first direction and the second direction, the conductive layers comprising word lines and a drain select gate line, and the drain select gate line being separated by a second dielectric layer in the second direction; and
a conductive portion disposed on and in direct contact with the second dielectric layer.
2 . The 3D memory device of claim 1 , wherein each of the memory arrays further comprises:
a first channel structure extending in the first direction through the word lines and the drain select gate line.
3 . The 3D memory device of claim 2 , wherein each of the memory arrays further comprises:
a second channel structure extending in the first direction through the word lines.
4 . The 3D memory device of claim 3 , wherein the second dielectric layer is disposed above the second channel structure and is in contact with the second channel structure.
5 . The 3D memory device of claim 3 , wherein a first length of the first channel structure in the first direction is larger than a second length of the second channel structure in the first direction.
6 . The 3D memory device of claim 3 , wherein each of the memory arrays further comprises:
a first semiconductor layer disposed above the first channel structure.
7 . The 3D memory device of claim 6 , wherein memory arrays comprise a first memory array and a second memory array disposed above the first memory array, and the second dielectric layer of the first memory array at least partially overlaps the second dielectric layer of the second memory array in a plan view of the 3D memory device.
8 . The 3D memory device of claim 7 , wherein the conductive portion of the first memory array at least partially overlaps the conductive portion of the second memory array in the plan view of the 3D memory device.
9 . A three-dimensional (3D) memory device, comprising:
a first stack structure comprising interleaved first conductive layers and first dielectric layers extending in a first direction and a second direction perpendicular to the first direction;
first channel structures extending in a third direction perpendicular to the first direction and the second direction through the first stack structure;
a second stack structure disposed above the first stack structure, comprising interleaved second conductive layers and second dielectric layers extending in the first direction and the second direction;
second channel structures extending in the third direction through the second stack structure;
a first cutting structure disposed between the first channel structures;
a second cutting structure disposed between the second channel structures;
a first dummy channel structure extending in the first stack structure in the third direction; and
a second dummy channel structure extending in the second stack structure in the third direction above the first dummy channel structure, wherein the first cutting structure is disposed between the first dummy channel structure and the second dummy channel structure; and
a first conductive portion disposed between the first cutting structure and the second dummy channel structure and in direct contact with the first cutting structure.
10 . The 3D memory device of claim 9 , wherein the first dummy channel structure, the first cutting structure, and the second dummy channel structure at least partially overlap in a plan view of the 3D memory device.
11 . The 3D memory device of claim 9 , wherein the first conductive layers of the first stack structure comprise word lines and a drain select gate line, and the drain select gate line being separated by the first cutting structure.
12 . The 3D memory device of claim 9 , wherein the second conductive layers of the second stack structure comprise word lines and a drain select gate line, and the drain select gate line being separated by the second cutting structure.
13 . The 3D memory device of claim 9 , further comprising:
a second conductive portion disposed on the second cutting structure.
14 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a first memory array comprising a first cutting structure between first channel structures and a conductive portion above and in direct contact with the first cutting structure; and
forming a second memory array above the first memory array, the second memory array comprising a second cutting structure between second channel structures.
15 . The method of claim 14 , wherein forming the first memory array comprising the first cutting structure between first channel structures and the conductive portion above and in direct contact with the first cutting structure, comprises:
forming a first dielectric stack comprising interleaved first dielectric layers and first sacrificial layers stacking in a first direction;
forming the first channel structures through the first dielectric stack in the first direction;
forming the first cutting structure in a topmost layer of the first sacrificial layers; and
forming the conductive portion above and in direct contact with the first cutting structure and the first channel structures.
16 . The method of claim 15 , further comprising:
replacing the first sacrificial layers with first conductive layers.
17 . The method of claim 15 , wherein forming the second memory array above the first memory array, comprises:
forming a second dielectric stack on the first memory array, the second dielectric stack comprising interleaved second dielectric layers and second sacrificial layers stacking in the first direction;
forming the second channel structures through the second dielectric stack in the first direction; and
forming the second cutting structure in a topmost layer of the second sacrificial layers.
18 . The method of claim 14 , wherein forming the first memory array comprising the first cutting structure between first channel structures and the conductive portion above and in direct contact with the first cutting structure, comprises:
forming a first stack structure comprising first word lines and a first drain select gate line, wherein the first word lines and the first drain select gate line stacking in a first direction;
forming the first cutting structure to cut the first drain select gate line; and
forming the first channel structure extending in the first direction in the first stack structure.
19 . The method of claim 18 , wherein forming the second memory array above the first memory array, comprises:
forming a second stack structure on the first stack structure, the second stack structure comprising second word lines and a second drain select gate line, wherein the second word lines and the second drain select gate line stacking in the first direction;
forming the second cutting structure to cut the second drain select gate line; and
forming the second channel structures extending in the first direction in the second stack structure.
20 . The method of claim 14 , wherein forming the second memory array above the first memory array, comprises:
forming the second cutting structure at least partially overlapping the first cutting structure in a plan view of the 3D memory device.