Semiconductor memory and nonvolatile memory
According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page size of input data corresponding to the external address.
1 . A nonvolatile memory comprising:
a plurality of memory cells configured to store three bits of data described by first to third bits and allocated to eight threshold areas that include a first threshold area indicating an erase area and second to eighth threshold areas each indicating write areas, threshold voltages of the second to eighth threshold areas being higher than a threshold voltage of the first threshold area, a g-th threshold area (g is a natural number from two to eight) indicating one of the second to eighth threshold areas having a higher threshold voltage than a (g−1)-th threshold area;
a word line coupled to the plurality of memory cells; and
a controller configured to execute a read operation with respect to the plurality of memory cells in response to a read command from an external controller, wherein
among first to seventh voltages existing between adjacent threshold areas of the first to eighth threshold areas, a number of voltages used for determining a value of data of the first bit is one, a number of voltages used for determining a value of data of the second bit is p (p is a natural number from two to four), and a number of voltages used for determining a value of data of the third bit is (6−p),
an address specified by the read command corresponds to one of a first page address and a second page address,
in a case where the specified address corresponds to the first page address, the controller is configured to read data from the plurality of memory cells by using a voltage used for determining the value of data of the first bit and the p voltages used for determining the value of data of the second bit among the first to seventh voltages, and
in a case where the specified address corresponds to the second page address, the controller is configured to read data from the plurality of memory cells by using a voltage used for determining the value of data of the first bit and the (6−p) voltages used for determining the value of data of the third bit among the first to seventh voltages.
2 . The nonvolatile memory according to claim 1 , wherein an h-th voltage (h is a natural number from two to seven) is higher than an (h−1)-th voltage, and the fourth voltage is used for determining the value of data of the first bit.
3 . The nonvolatile memory according to claim 2 , wherein the p is three.
4 . The nonvolatile memory according to claim 3 , wherein
the first voltage, the third voltage, and the sixth voltage are used for determining the value of data of the second bit, and
the second voltage, the fifth voltage, and the seventh voltage are used for determining the value of data of the third bit.
5 . The nonvolatile memory according to claim 2 , wherein the p is four.
6 . The nonvolatile memory according to claim 5 , wherein
the first voltage, the third voltage, the fifth voltage, and the seventh voltage are used for determining the value of data of the second bit, and
the second voltage and the sixth voltage are used for determining the value of data of the third bit.
7 . The nonvolatile memory according to claim 2 , wherein the p is two.
8 . The nonvolatile memory according to claim 7 , wherein
the second voltage and the sixth voltage are used for determining the value of data of the second bit, and
the first voltage, the third voltage, the fifth voltage, and the seventh voltage are used for determining the value of data of the third bit.
9 . The nonvolatile memory according to claim 1 , wherein
the data read from the plurality of memory cells by using the voltage used for determining the value of data of the first bit and the p voltages used for determining the value of data of the second bit includes first data and second data,
the first data is read from the plurality of memory cells by using the voltage used for determining the value of data of the first bit,
the second data is read from the plurality of memory cells by using the p voltages used for determining the value of data of the second bit includes first data and second data, and
the controller is configured to send the first data and the second data in response to the read command specifying the first page address.
10 . The nonvolatile memory according to claim 9 , wherein
the data read from the plurality of memory cells by using the voltage used for determining the value of data of the first bit and the (6−p) voltages used for determining the value of data of the third bit includes third data and fourth data,
the third data is read from the plurality of memory cells by using the voltage used for determining the value of data of the first bit,
the fourth data is read from the plurality of memory cells by using the (6−p) voltages used for determining the value of data of the third bit, and
the controller is configured to send the third data and the fourth data in response to the read command specifying the second page address.
11 . The nonvolatile memory according to claim 10 , wherein
a size of the first data is smaller than a size of the second data, and
a size of the third data is smaller than a size of the fourth data.
12 . The nonvolatile memory according to claim 11 , wherein
the size of the second data is equal to the size of the fourth data.
13 . The nonvolatile memory according to claim 11 , wherein
a sum of the size of the first data and the size of the third data is equal to the size of the second data.
14 . The nonvolatile memory according to claim 11 , wherein
a sum of the size of the first data and the size of the third data is equal to the size of the fourth data.
15 . The nonvolatile memory according to claim 10 , further comprising:
a plurality of first latch circuits;
a plurality of second latch circuits; and
a plurality of third latch circuits, wherein
in response to the read command specifying the first page address,
the data read from the plurality of memory cells by using the voltage used for determining the value of data of the first bit is stored into the plurality of first latch circuits and the plurality of second latch circuits,
the data stored in the plurality of first latch circuits is stored into the plurality of third latch circuits, and
the controller is configured to send the data stored in the plurality of third latch circuits as the first data.
16 . The nonvolatile memory according to claim 15 , wherein, in response to the read command specifying the second page address,
the data read from the plurality of memory cells by using the voltage used for determining the value of data of the first bit is stored into the plurality of first latch circuits and the plurality of second latch circuits,
the data stored in the plurality of second latch circuits is stored into the plurality of third latch circuits, and
the controller is configured to send the data stored in the plurality of third latch circuits as the third data.
17 . The nonvolatile memory according to claim 16 , wherein, in response to the read command specifying the first page address,
the data read from the plurality of memory cells by using the p voltages used for determining the value of data of the second bit is stored into the plurality of first latch circuits and the plurality of second latch circuits,
the data stored in the plurality of first latch circuits and the plurality of second latch circuits is stored into the plurality of third latch circuits, and
the controller is configured to send the data stored in the plurality of third latch circuits as the second data.
18 . The nonvolatile memory according to claim 16 , wherein, in response to the read command specifying the second page address,
the data read from the plurality of memory cells by using the (6−p) voltages used for determining the value of data of the third bit is stored into the plurality of first latch circuits and the plurality of second latch circuits,
the data stored in the plurality of first latch circuits and the plurality of second latch circuits is stored into the plurality of third latch circuits, and
the controller is configured to send the data stored in the plurality of third latch circuits as the fourth data.