Granted Patent B2

US 12,633,370 · App. 18/755,329 · Granted May 19, 2026

Inventors: Chun-Hsiung Hung (Hsinchu, TW); Hsin-Yi Ho (Hsinchu, TW)

Assignee: MACRONIX INTERNATIONAL CO., LTD.

G11C29/702G11C11/54G11C29/789

Abstract

Claims (59)

1 . A compute-in-memory device, comprising:

control circuits providing N input data elements and M redundancy input data elements, N and M being integers greater than zero;

multiplier circuits configured to (i) multiply the N input data elements by N stored data elements and (ii) provide a multiplier output; and

redundancy multiplier circuits configured to (i) multiply the M redundancy input data elements by M stored redundant data elements and (ii) provide a redundancy multiplier output, wherein the control circuits include logic to execute operations including providing (i) the N input data elements to the multiplier circuits and (ii) the M redundancy input data elements with a value of zero to the redundancy multiplier circuits, such that the redundancy multiplier circuits provide a redundancy multiplier output of zero, regardless of a value of the M stored redundant data elements.

2 . The compute-in-memory device of claim 1 , further comprising an accumulation circuitry receiving the multiplier output and the redundancy multiplier output and configured to generate a sum of (i) data elements of the received multiplier output and (ii) data elements of the received redundancy multiplier output.

3 . The compute-in-memory device of claim 1 , wherein the operations further include, responsive to an indication of a defective column:

providing, to a redundancy multiplier circuit of the redundancy multiplier circuits, a value of a particular input data element originally allocated to a multiplier circuit, of the multiplier circuits, connected to the defective column; and

providing a value of zero as an input data element to the multiplier circuit connected to the defective column.

4 . The compute-in-memory device of claim 3 , further comprising:

an array of N memory cells storing the N stored data elements and including the defective column; and

an array of M redundant memory cells storing the M stored redundant data elements, wherein a data element of the N stored data elements originally addressed to a memory cell, of the N memory cells, that is connected to the defective column is provided to a redundant memory cell of the M redundant memory cells as a redundant data element of the M stored redundant data elements, and

wherein the redundancy multiplier circuit (i) multiplies the redundant data element of the redundant memory cell by the value of the particular input data element originally allocated to the multiplier circuit connected to the defective column and (ii) provides a product of the multiplication as a data element of the redundancy multiplier output.

5 . The compute-in-memory device of claim 4 , wherein the array of N memory cells includes static random access memory (SRAM).

6 . The compute-in-memory device of claim 4 , wherein the array of N memory cells includes dynamic random access memory (DRAM).

7 . The compute-in-memory device of claim 4 , wherein the array of N memory cells includes non-volatile memory.

8 . The compute-in-memory device of claim 4 , further comprising an accumulation circuitry receiving the multiplier output and the redundancy multiplier output and configured to generate a sum of data elements of the received multiplier output and data elements of the received redundancy multiplier output.

9 . The compute-in-memory device of claim 3 ,

wherein the control circuits include buffers for storing values of the N input data elements and values of the M redundancy input data elements, and

wherein the operations include changing the values of the N input data elements and the values of the M redundancy input data elements in dependence upon the indication of the defective column.

10 . The compute-in-memory device of claim 1 , wherein the N input data elements are activator inputs of a neural network and the N stored data elements are weights of a neural network.

11 . The compute-in-memory device of claim 1 , wherein the operations further include, responsive to an indication of two defective columns:

providing, to a first redundancy multiplier circuit of the redundancy multiplier circuits, a value of a first particular input data element originally allocated to a multiplier circuit, of the multiplier circuits, connected to a first defective column of the two defective columns;

providing, to a second redundancy multiplier circuit of the redundancy multiplier circuits, a value of a second particular input data element originally allocated to a multiplier circuit, of the multiplier circuits, connected to a second defective column of the two defective columns; and providing a value of zero as an input data element to the multiplier circuit connected to the first defective column and to the multiplier circuit connected to the second defective column.

12 . A method of performing operations using a compute-in-memory device including

(i) control circuits providing N input data elements and M redundancy input data elements, N and M being integers greater than zero, (ii) multiplier circuits configured to multiply the N input data elements by N stored data elements and provide a multiplier output, and (iii) redundancy multiplier circuits configured to multiply the M redundancy input data elements by M stored redundant data elements and provide a redundancy multiplier output, the method comprising:

providing the N input data elements to the multiplier circuits; and

providing the M redundancy input data elements with a value of zero as an input data element to the redundancy multiplier circuits, such that the redundancy multiplier circuits provide a redundancy multiplier output of zero, regardless of a value of the M stored redundant data elements.

13 . The method of claim 12 , further comprising generating a sum of (i) data elements of the multiplier output and (ii) data elements of the redundancy multiplier output.

14 . The method of claim 12 , further comprising:

receiving an indication that there is a defective column in a memory array of the compute-in-memory device;

providing, to a redundancy multiplier circuit of the redundancy multiplier circuits, a value of a particular input data element originally allocated to a multiplier circuit, of the multiplier circuits, connected to the defective column; and

providing a value of zero as an input data element to the multiplier circuit connected to the defective column.

15 . The method of claim 14 ,

wherein the compute-in-memory device further includes an array of N memory cells storing the N stored data elements and including the defective column, and an array of M redundant memory cells storing the M stored redundant data elements, and

wherein the method further includes:

providing a data element, of the N stored data elements, originally addressed to a memory cell of the N memory cells that is connected to the defective column to a redundant memory cell of the M redundant memory cells as a redundant data element of the M stored redundant data elements;

multiplying, by the redundancy multiplier circuit, the redundant data element of the redundant memory cell by the value of the particular input data element originally allocated to the multiplier circuit connected to the defective column; and

providing, by the redundancy multiplier circuit, a product of the multiplication as a data element of the redundancy multiplier output.

16 . The method of claim 12 , further comprising:

receiving an indication that there are two defective columns in a memory array of the compute-in-memory device;

providing, to a first redundancy multiplier circuit of the redundancy multiplier circuits, a value of a first particular input data element originally allocated to a multiplier circuit, of the multiplier circuits, connected to a first defective column of the two defective columns;

providing, to a second redundancy multiplier circuit of the redundancy multiplier circuits, a value of a second particular input data element originally allocated to a multiplier circuit, of the multiplier circuits, connected to a second defective column of the two defective columns; and

providing a value of zero as an input data element to the multiplier circuit connected to the first defective column and to the multiplier circuit connected to the second defective column.

17 . A compute-in-memory device, comprising:

control circuits providing N input data elements and M redundancy input data elements, N and M being integers greater than zero;

multiplier circuits configured to (i) multiply the N input data elements by N stored data elements and (ii) provide a multiplier output; and

redundancy multiplier circuits configured to (i) multiply the M redundancy input data elements by M stored redundant data elements and (ii) provide a redundancy multiplier output, wherein the control circuits include logic to execute operations including, responsive to an indication of a defective column in a memory array storing stored data elements:

providing, to a redundancy multiplier circuit of the redundancy multiplier circuits, a value of a particular input data element originally allocated to a multiplier circuit, of the multiplier circuits, connected to the defective column; and

providing a value of zero as an input data element to the multiplier circuit connected to the defective column, such that the multiplier circuit connected to the defective column provides a multiplier output of zero for the defective column, regardless of a value of a stored data element of the defective column.

18 . The compute-in-memory device of claim 17 , further comprising an accumulation circuitry receiving the multiplier output and the redundancy multiplier output and configured to generate a sum of (i) data elements of the received multiplier output and (ii) data elements of the received redundancy multiplier output.

19 . The compute-in-memory device of claim 17 , further comprising:

an array of N memory cells storing the N stored data elements and including the defective column; and

an array of M redundant memory cells storing the M stored redundant data elements,

wherein a data element of the N stored data elements originally addressed to a memory cell, of the N memory cells, that is connected to the defective column is provided to a redundant memory cell of the M redundant memory cells as a redundant data element of the M stored redundant data elements, and

wherein the redundancy multiplier circuit (i) multiplies the redundant data element of the redundant memory cell by the value of the particular input data element originally allocated to the multiplier circuit connected to the defective column and (ii) provides a product of the multiplication as a data element of the redundancy multiplier output.

20 . The compute-in-memory device of claim 17 , wherein the operations further include, responsive to an indication of two defective columns:

providing, to a first redundancy multiplier circuit of the redundancy multiplier circuits, a value of a first particular input data element originally allocated to a multiplier circuit, of the multiplier circuits, connected to a first defective column of the two defective columns;

providing, to a second redundancy multiplier circuit of the redundancy multiplier circuits, a value of a second particular input data element originally allocated to a multiplier circuit, of the multiplier circuits, connected to a second defective column of the two defective columns; and

providing a value of zero as an input data element to the multiplier circuit connected to the first defective column and to the multiplier circuit connected to the second defective column.

Assignments (1)

Continuity (1)

References Cited (42)