IP Library › Granted Patent US 12,633,663
Granted Patent B2
US 12,633,663 · App. 18/673,910 · Granted May 19, 2026

Intelligent reflecting surface

Inventors: Daiichi Suzuki (Tokyo, JP); Shinichiro Oka (Tokyo, JP); Shigesumi Araki (Tokyo, JP); Mitsutaka Okita (Tokyo, JP)
Assignee: Japan Display Inc.
H01Q3/46G02F1/134336H01Q3/36H01Q15/148
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,633,663
App. No.
18/673,910
Granted
May 19, 2026
Kind
B2
Abstract

According to one embodiment, an intelligent reflecting surface includes a plurality of individual areas, each of the individual areas including a first area and one or more second areas, a connection area, a first substrate including a plurality of patch electrodes, a second substrate including a common electrode, the common electrode being located in the first area of each of the individual areas and the connection area and being opposed to the patch electrodes, and a liquid crystal layer held between the first substrate and the second substrate and opposed to the patch electrodes.

Claims (44)

1 . An intelligent reflecting surface, comprising:

a plurality of individual areas arranged in a matrix along each of an X-axis and a Y-axis orthogonal to each other, each of the plurality of individual areas including a first area and one or more second areas other than the first area;

a connection area located in gaps between the plurality of individual areas, the connection area having a grating shape and being connected to the plurality of individual areas;

a first substrate including a plurality of patch electrodes, each of the plurality of patch electrodes being located in the first area of a corresponding individual area among the plurality of individual areas;

a second substrate including a common electrode, the common electrode being located in the first area of each of the plurality of individual areas and the connection area and being opposed to the plurality of patch electrodes in a direction parallel to a Z-axis orthogonal to each of the X-axis and the Z-axis;

a liquid crystal layer held between the first substrate and the second substrate and opposed to the plurality of patch electrodes,

the first area is a cross-shaped area and includes a first linear area extending in a direction parallel to the X-axis and a second linear area extending in a direction parallel to the Y-axis and intersecting the first linear area,

each of the plurality of patch electrodes has a cross shape and is located in the first area, and

a portion of the common electrode, which is located in each of the plurality of individual areas, has the cross shape and is located in the first area.

2 . The intelligent reflecting surface according to claim 1 , wherein

each of the plurality of patch electrodes and the common electrode is formed of a metal.

3 . The intelligent reflecting surface according to claim 1 , wherein

a shape of a portion of the common electrode, which is located in each of the plurality of individual areas, is the same as a shape of each of the plurality of patch electrodes, and

the portion of the common electrode, which is located in each of the plurality of individual areas, overlaps with a corresponding patch electrode among the plurality of patch electrodes in plan view.

4 . The intelligent reflecting surface according to claim 1 , wherein

each of the plurality of patch electrodes includes:

a plurality of first linear electrodes located in the first linear area, extending in the direction parallel to the X-axis, and arranged at intervals in the direction parallel to the Y-axis; and

a plurality of second linear electrodes located in the second linear area, extending in the direction parallel to the Y-axis, arranged at intervals in the direction parallel to the X-axis, intersecting the plurality of first linear electrodes, and formed integrally with the plurality of first linear electrodes, and

a portion of the common electrode, which is located in each of the plurality of individual areas, includes:

a plurality of third linear electrodes located in the first linear area and extending parallel to the plurality of first linear electrodes; and

a plurality of fourth linear electrodes located in the second linear area, extending parallel to the plurality of second linear electrodes, intersecting the plurality of third linear electrodes, and formed integrally with the plurality of third linear electrodes.

5 . The intelligent reflecting surface according to claim 1 , wherein

a shape of each of the plurality of patch electrodes and a portion of the common electrode located in each of the plurality of individual areas is rotational symmetry at 90 degrees in plan view.

6 . The intelligent reflecting surface according to claim 5 , wherein

the shape is square.

7 . An intelligent reflecting surface comprising:

a plurality of individual areas arranged in a matrix along each of an X-axis and a Y-axis orthogonal to each other, each of the plurality of individual areas including a first area and one or more second areas other than the first area;

a connection area located in gaps between the plurality of individual areas, the connection area having a grating shape and being connected to the plurality of individual areas;

a first substrate including a plurality of patch electrodes, each of the plurality of patch electrodes being located in the first area of a corresponding individual area among the plurality of individual areas;

a second substrate including a common electrode, the common electrode being located in the first area of each of the plurality of individual areas and the connection area and being opposed to the plurality of patch electrodes in a direction parallel to a Z-axis orthogonal to each of the X-axis and the Z-axis; and

a liquid crystal layer held between the first substrate and the second substrate and opposed to the plurality of patch electrodes,

wherein

the first area is a square grating-shaped area and includes a frame-shaped area and a grating-shaped area surrounded by the frame-shaped area and connected to the frame-shaped area,

the grating-shaped area includes:

a plurality of first linear areas extending in the direction parallel to the X-axis and arranged at intervals in the direction parallel to the Y-axis; and

a plurality of second linear areas extending in the direction parallel to the Y-axis, arranged at intervals in the direction parallel to the X-axis, and intersecting the plurality of first linear areas,

each of the plurality of patch electrodes includes:

a first frame-shaped electrode located in the frame-shaped area and having a frame shape;

a plurality of first linear electrodes located in the plurality of first linear areas in a one-to-one correspondence and extending in the direction parallel to the X-axis; and

a plurality of second linear electrodes located in the plurality of second linear areas in a one-to-one correspondence and extending in the direction parallel to the Y-axis, intersecting the plurality of first linear electrodes, and formed integrally with the first frame-shaped electrode and the plurality of first linear electrodes, and

a portion of the common electrode, which is located in each of the plurality of individual areas, includes:

a second frame-shaped electrode located in the frame-shaped area and extending parallel to the first frame-shaped electrode;

a plurality of third linear electrodes located in the plurality of first linear areas in a one-to-one correspondence and extending parallel to the plurality of first linear electrodes; and

a plurality of fourth linear electrodes located in the plurality of second linear areas in a one-to-one correspondence, extending parallel to the plurality of second linear electrodes, intersecting the plurality of third linear electrodes, and formed integrally with the second frame-shaped electrode and the plurality of third linear electrodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2024
From: SUZUKI, DAIICHI; OKA, SHINICHIRO; ARAKI, SHIGESUMI; OKITA, MITSUTAKA
To: JAPAN DISPLAY INC.
Reel/Frame 067889/0967 →
Priority Claims (1)
JP 2021-191313 · Nov 25, 2021 · national
Continuity (2)
Continuation PCTJP2022040674 · Oct 31, 2022
Related Publication 20240322429A1 · Sep 26, 2024
References Cited (6)
US 20150380789A1 · Jakoby · 2015 [cited by examiner]
US 20180083364A1 · Foo · 2018 [cited by applicant]
US 20210408680A1 · Xi · 2021 [cited by examiner]
US 20240243473A1 · Lee · 2024 [cited by examiner]
JP H11103201A · 1999 [cited by applicant]
JP 2019530387A · 2019 [cited by applicant]