Dual multi-level inverter topology with reduced switch count and small DC-link capacitor
A dual multi-level inverter topology with reduced switch count and small DC-link capacitor is provided. The inverter topology provides multi-level inverter operation without requiring a neutral point connection that is commonly present in a stacked capacitor topology (for example, a topology including two capacitors).
1 . A multi-level inverter comprising:
a first circuit comprising a first set of one or more switches with a first output node and a second output node;
a second circuit comprising a second set of one or more switches with a third output node and a fourth output node;
a third circuit comprising a third set of one or more switches with a fifth output node and a sixth output node, wherein the first output node, the third output node, and the fifth output node form a first three-phase output, wherein each of the first, the third, and the fifth output nodes are configured to independently generate a first non-zero voltage, a second non-zero voltage, and a first zero voltage, wherein the second output node, the fourth output node, and the sixth output node form a second three-phase output, and wherein each of the second, the fourth, and the sixth output nodes are configured to independently generate a third non-zero voltage, a fourth non-zero voltage, and a second zero voltage;
a first balanced three-phase load configured to receive three outputs from the first three-phase output; and
a second balanced three-phase load configured to receive three outputs from a second three-phase output, wherein the first balanced three-phase load and the second balanced three-phase load form active neutral points.
2 . The multi-level inverter of claim 1 , wherein the first set of one or more switches, the second set of one or more switches, and the third set of one or more switches are each provided in a neutral-point-less (NPL) H-type configuration or an NPL X-type configuration.
3 . The multi-level inverter of claim 1 , further comprising:
a controller comprising:
memory that stores computer-executable instructions; and
one or more processors configured to access the memory and execute the computer-executable instructions to:
cause, at a first time, a first switch and second switch of the first set of one or more switches to close;
cause, at a second time, a third switch and fourth switch of the first set of one or more switches to close; and
cause, at a third time, at least one of a fifth switch and a sixth switch of the first set of one or more switches to close.
4 . The multi-level inverter of claim 1 , wherein the one or more switches are transistors.
5 . The multi-level inverter of claim 1 , wherein the first balanced three-phase load and the second balanced three-phase load are 180 degrees phase shifted with two separate neutral points, and wherein the first and second zero voltages are only generated by a combination of two or more instances of the first, the second, and the third circuits as well as both of the first and the second balanced three-phase loads.
6 . The multi-level inverter of claim 1 , further comprising one or more capacitors connected in parallel with an input of the multi-level inverter without a neutral point connection.
7 . A system comprising:
a direct current (DC) power source;
a multi-level inverter configured to receive a DC signal from the DC power source, the multi-level inverter comprising:
a first circuit comprising a first set of one or more switches with a first output node and a second output node;
a second circuit comprising a second set of one or more switches with a third output node and a fourth output node;
a third circuit comprising a third set of one or more switches with a fifth output node and a sixth output node, wherein the first output node, the third output node, and the fifth output node form a first three-phase output, wherein each of the first, the third, and the fifth output nodes are configured to independently generate a first non-zero voltage, a second non-zero voltage, and a first zero voltage, wherein the second output node, the fourth output node, and the sixth output node form a second three-phase output, and wherein each of the second, the fourth, and the sixth output nodes are configured to independently generate a third non-zero voltage, a fourth non-zero voltage, and a second zero voltage;
a first balanced three-phase load configured to receive three outputs from the first three-phase output; and
a second balanced three-phase load configured to receive three outputs from a second three-phase output, wherein the first balanced three-phase load and the second balanced three-phase load form active neutral points.
8 . The system of claim 7 , wherein the first set of one or more switches, the second set of one or more switches, and the third set of one or more switches are each provided in a neutral-point-less (NPL) H-type configuration or an NPL X-type configuration.
9 . The system of claim 7 , further comprising:
a controller comprising:
memory that stores computer-executable instructions; and
one or more processors configured to access the memory and execute the computer-executable instructions to:
cause, at a first time, a first and second switch of the first set of one or more switches to close;
cause, at a second time, a third and fourth switch of the first set of one or more switches to close; and
cause, at a third time, at least one of a fifth and a sixth switch of the first set of one or more switches to close.
10 . The system of claim 7 , wherein the one or more switches are transistors.
11 . A method comprising:
receiving a direct current (DC) signal at an input of a multi-level power inverter, wherein the multi-level power inverter includes a first circuit comprising a first set of one or more switches with a first output node and a second output node, a second circuit comprising a second set of one or more switches with a third output node and a fourth output node, and a third circuit comprising a third set of one or more switches with a fifth output node and a sixth output node, wherein the first output node, the third output node, and the fifth output node form a first three-phase output, and wherein the second output node, the fourth output node, and the sixth output node form a second three-phase output;
independently generating, by each of the first, the third, and the fifth output nodes, a third non-zero voltage, a fourth non-zero voltage, and a second zero voltage;
independently generating, by each of the second, the fourth, and the sixth output nodes, a third non-zero voltage, a fourth non-zero voltage, and a second zero voltage;
receiving, by a first balanced three-phase load, three outputs from the first three-phase output; and
receiving, by a second balanced three-phase load, three outputs from the second three-phase output, wherein the first three-phase load and the second three-phase load form active neutral points.