Isolated gate driver
Described is circuitry ( 200 ) for driving a power switching device ( 226 ), the circuitry ( 200 ) comprising: a control circuit ( 211 ) in a first power domain configured to generate a first power domain PWM pulse signal ( 208 a, 208 b, 208 c, 208 d ) in response to received PWM pulse data ( 207 a, 207 b, 207 c, 207 d ) that encodes a PWM waveform, the first power domain PWM pulse signal ( 208 a, 208 b, 208 c, 208 d ) being synchronous with a system clock signal ( 210 ); an isolation coupler ( 214, 218 a, 218 b, 218 c, 218 d ) between the first power domain and a second power domain configured to generate a second power domain PWM pulse signal ( 209 a, 209 b, 209 c, 209 d ) in response to the first power domain PWM pulse signal ( 208 a, 208 b, 208 c, 208 d ); and a drive circuit ( 212 ) in the second power domain configured to drive the power switching device ( 226 ) with a voltage input ( 201, 202, 203, 225 ) in response to the second power domain PWM pulse signal ( 209 a, 209 b, 209 c, 209 d ).
1 . Circuitry configured to drive a power switching device, the circuitry comprising:
a control circuit in a first power domain configured to generate a first power domain PWM pulse signal in response to received PWM pulse data that encodes a PWM waveform, the first power domain PWM pulse signal being synchronous with a system clock signal;
an isolation coupler between the first power domain and a second power domain configured to generate a second power domain PWM pulse signal in response to the first power domain PWM pulse signal; and
a drive circuit in the second power domain configured to drive the power switching device with a voltage input in response to the second power domain PWM pulse signal.
2 . The circuitry according to claim 1 , wherein the control circuit is configured to generate the PWM pulse data by encoding input command data, the input command data comprising a numerical representation of the PWM duty cycle.
3 . The circuitry according to claim 1 , wherein the PWM pulse data comprises ON data sets representing an ON PWM waveform and OFF data sets representing an OFF PWM waveform.
4 . The circuitry according to claim 3 , wherein the ON data sets comprise an ON_START data set representing a start time of the ON PWM waveform and an ON_END data set representing an end time of the ON PWM waveform, and the OFF data sets comprise an OFF_START data set representing a start time of the OFF PWM waveform and an OFF_END data set representing an end time of the OFF PWM waveform.
5 . The circuitry according to claim 3 , wherein the control circuit is configured to generate a plurality of first power domain PWM pulse signals, each first power domain PWM pulse signal being generated in response to a corresponding PWM pulse data set.
6 . The circuitry according to claim 5 , wherein the isolation coupler is configured to generate a plurality of second power domain PWM pulse signals, each second power domain PWM pulse signal being generated in response to a corresponding first power domain PWM pulse signal.
7 . The circuitry according to claim 6 , wherein the isolation coupler comprises a plurality of transformers, each transformer configured to generate a second power domain PWM pulse signal of the plurality of second power domain PWN pulse signals.
8 . The circuitry according to claim 6 , wherein the drive circuit is configured to drive the power switching device with the voltage input in response to the plurality of second power domain PWM pulse signals.
9 . The circuitry according to claim 6 , wherein the drive circuit comprises an ON gate, the ON gate closing in response to an ON_START second power domain PWM pulse signal and opening in response to an ON_END second power domain PWM pulse signal.
10 . The circuitry according to claim 9 , wherein the voltage input to the power switching device increases in response to the ON gate closing.
11 . The circuitry according to claim 9 , wherein the second power domain comprises a first sub-power domain and a second sub-power domain.
12 . The circuitry according to claim 11 , wherein the ON gate is located in the first sub-power domain and the OFF gate is located in the second sub-power domain.
13 . The circuitry according to claim 6 , wherein the drive circuit comprises an OFF gate, the OFF gate closing in response to an OFF_START second power domain PWM pulse signal and opening in response to an OFF_END second power domain PWM pulse signal.
14 . The circuitry according to claim 13 , wherein the voltage input to the power switching device decreases in response to the OFF gate closing.
15 . The circuitry according to claim 1 , wherein the isolation coupler comprises at least one transformer.
16 . The circuitry according to claim 1 , wherein the control circuit is configured to receive a first power domain voltage input, the isolation coupler is configured to generate a second power domain voltage input in response to the first power domain voltage input, and the drive circuit is configured to generate a power switching device voltage input from the second power domain voltage input, the power switching device voltage input being used to drive the power switching device.
17 . The circuitry according to claim 1 , wherein: the circuitry comprises a plurality of power switching devices driven by the drive circuit, and wherein the plurality of power switching devices comprises a transistor and/or a field effect transistor.
18 . A power converter assembly comprising a power converter driven by the circuitry of claim 1 .
19 . An electric motor assembly comprising an electric motor driven by the circuitry of claim 1 .