IP Library › Granted Patent US 12,633,942
Granted Patent B2
US 12,633,942 · App. 18/790,695 · Granted May 19, 2026

Encoding method, encoder and data transmission system

Inventor: Chunpo Pan (Ottawa, CA)
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
H03M13/05H04L1/0041H04L1/0045H04L1/0057
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,633,942
App. No.
18/790,695
Granted
May 19, 2026
Kind
B2
Abstract

An encoding method, applied to the field of encoding technologies, may be used for reducing the delay and reducing the decoding memory, and includes: obtaining a data signal including a plurality of information bits; and performing encoding process on the data signal to obtain an encoded signal. An encoding block in the encoded signal includes a first encoding sub-block and at least one second encoding sub-block. The first encoding sub-block includes first component codewords and second component codewords, and all information bits constitute an information bit matrix. Each second encoding sub-block includes a first check matrix, which includes first check bit sets each determined based on bits of a first bit matrix with same side lengths, and the first check bit set and the bits of the first bit matrix constitute a third component codeword.

Claims (54)

1 . A method, comprising:

obtaining a data signal, the data signal including a plurality of information bits; and

performing an encoding process on the data signal to obtain an encoded signal, wherein;

the encoded signal includes at least one encoding block, and an encoding block includes a first encoding sub-block and at least one second encoding sub-block;

the first encoding sub-block includes a plurality of first component codewords and a plurality of second component codewords, a first component codeword and a second component codeword both include one or more information bits of the plurality of information bits and one or more check bits, and all information bits in the plurality of first component codewords and the plurality of second component codewords constitute an information bit matrix; and

each second encoding sub-block includes a first check matrix; the first check matrix includes a plurality of first check bit sets each including one or more check bits, a first check bit set is determined based on bits of a first bit matrix with same side lengths, and the first check bit set and the bits of the first bit matrix constitute a third component codeword; and

wherein the first bit matrix includes any one of: part or all of information bits of the plurality of information bits, part or all of check bits in the plurality of first component codewords, or part or all of check bits in the plurality of second component codewords.

2 . The method according to claim 1 , wherein no two bits in the first bit matrix share same two third component codewords.

3 . The method according to claim 1 , wherein the first encoding sub-block has same side lengths, and a side length of the first bit matrix is less than or equal to a side length of the first encoding sub-block; or

the first encoding sub-block has different side lengths, and a side length of the first bit matrix is less than or equal to a minimum side length of the first encoding sub-block.

4 . The method according to claim 1 , wherein the third component codeword includes bits in a row or column selected from a second bit matrix, and the second bit matrix is determined based on the first bit matrix and an invertible transformation matrix; and

bits in different third component codewords are bits in a row or column selected from different second bit matrices.

5 . The method according to claim 1 , wherein the second encoding sub-block further includes a second check matrix, and the second check matrix is used to correct errors in check bits of the first check matrix.

6 . The method according to claim 5 , wherein the second check matrix includes a plurality of second check bit sets, each second check bit set includes one or more check bits, and the second check bit set is determined based on a plurality of check bits of the first check matrix.

7 . The method according to claim 6 , wherein the at least one second encoding sub-block and the first encoding sub-block are in a same column but in different rows, and the first check matrix and the second check matrix are in a same row but in different columns; and

the second check matrix includes the plurality of second check bit sets each including one or more check bits, and the second check bit set is determined based on a row of check bits in the first check matrix, and check bits in the row of check bits are located in the plurality of first check bit sets.

8 . The method according to claim 7 , wherein the at least one second encoding sub-block includes a plurality of second encoding sub-blocks, and the plurality of second encoding sub-blocks are located on a same side or on opposite sides of the first encoding sub-block.

9 . The method according to claim 6 , wherein the at least one second encoding sub-block and the first encoding sub-block are in a same row but in different columns, and the first check matrix and the second check matrix are in a same column but in different rows; and

the second check matrix includes the plurality of second check bit sets each including one or more check bits, and the second check bit set is determined based on a column of check bits in the first check matrix, and check bits in the column of check bits are located in the plurality of first check bit sets.

10 . An encoder, comprising:

an interface circuit configured to obtain a data signal, the data signal including a plurality of information bits; and

a processor configured to perform an encoding process on the data signal to obtain an encoded signal, wherein:

the encoded signal includes at least one encoding block, and an encoding block includes a first encoding sub-block and at least one second encoding sub-block;

the first encoding sub-block includes a plurality of first component codewords and a plurality of second component codewords; a first component codeword and a second component codeword both include one or more information bits of the plurality of information bits and one or more check bits, and all information bits in the plurality of first component codewords and the plurality of second component codewords constitute an information bit matrix; and

each second encoding sub-block includes a first check matrix; the first check matrix includes a plurality of first check bit sets each including one or more check bits, a first check bit set is determined based on bits of a first bit matrix with same side lengths, and the first check bit set and the bits of the first bit matrix constitute a third component codeword; and

wherein the first bit matrix includes any one of: part or all of information bits of the plurality of information bits, part or all of check bits in the plurality of first component codewords, or part or all of check bits in the plurality of second component codewords.

11 . The encoder according to claim 10 , wherein no two bits in the first bit matrix share same two third component codewords.

12 . The encoder according to claim 10 , wherein the first encoding sub-block has same side lengths, and a side length of the first bit matrix is less than or equal to a side length of the first encoding sub-block; or

the first encoding sub-block has different side lengths, and a side length of the first bit matrix is less than or equal to a minimum side length of the first encoding sub-block.

13 . The encoder according to claim 10 , wherein the third component codeword includes bits in a row or column selected from a second bit matrix, and the second bit matrix is determined based on the first bit matrix and an invertible transformation matrix; and

bits in different third component codewords are bits in a row or column selected from different second bit matrices.

14 . The encoder according to claim 10 , wherein the second encoding sub-block further includes a second check matrix, and the second check matrix is used to correct errors in check bits of the first check matrix.

15 . The encoder according to claim 14 , wherein the second check matrix includes a plurality of second check bit sets, each second check bit set includes one or more check bits, and the second check bit set is determined based on a plurality of check bits of the first check matrix.

16 . The encoder according to claim 15 , wherein the at least one second encoding sub-block and the first encoding sub-block are in a same column but in different rows, and the first check matrix and the second check matrix are in a same row but in different columns; and the second check matrix includes the plurality of second check bit sets each including one or more check bits, the second check bit set is determined based on a row of check bits in the first check matrix, and check bits in the row of check bits are located in the plurality of first check bit sets; or

the at least one second encoding sub-block and the first encoding sub-block are in a same row but in different columns, and the first check matrix and the second check matrix are in a same column but in different rows; and the second check matrix includes the plurality of second check bit sets each including one or more check bits, and the second check bit set is determined based on a column of check bits in the first check matrix, and check bits in the column of check bits are located in the plurality of first check bit sets.

17 . The encoder according to claim 16 , wherein the at least one second encoding sub-block includes a plurality of second encoding sub-blocks, and the plurality of second encoding sub-blocks are located on a same side or on opposite sides of the first encoding sub-block.

18 . A data transmission system, comprising:

a transmitter including an encoder, the encoder comprising:

an interface circuit configured to obtain a data signal, the data signal including a plurality of information bits; and

a processor configured to perform an encoding process on the data signal to obtain an encoded signal, wherein:

the encoded signal includes at least one encoding block, and an encoding block includes a first encoding sub-block and at least one second encoding sub-block;

the first encoding sub-block includes a plurality of first component codewords and a plurality of second component codewords; a first component codeword and a second component codeword both include one or more information bits of the plurality of information bits and one or more check bits, and all information bits in the plurality of first component codewords and the plurality of second component codewords constitute an information bit matrix; and

each second encoding sub-block includes a first check matrix; the first check matrix includes a plurality of first check bit sets each including one or more check bits, a first check bit set is determined based on bits of a first bit matrix with same side lengths, and the first check bit set and the bits of the first bit matrix constitute a third component codeword; and

wherein the first bit matrix includes any one of: part or all of information bits of the plurality of information bits, part or all of check bits in the plurality of first component codewords, or part or all of check bits in the plurality of second component codewords;

the transmitter being configured to transmit the encoded signal; and

a receiver coupled to the transmitter and including a decoder, the receiver being configured to receive the encoded signal and use the decoder to decode the encoded signal.

19 . The data transmission system according to claim 18 , wherein the decoder is a hard decoder or soft decoder.

20 . A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, causes the computer to perform operations including:

obtaining a data signal, the data signal including a plurality of information bits; and

performing an encoding process on the data signal to obtain an encoded signal, wherein:

the encoded signal includes at least one encoding block, and an encoding block includes a first encoding sub-block and at least one second encoding sub-block;

the first encoding sub-block includes a plurality of first component codewords and a plurality of second component codewords, a first component codeword and a second component codeword both include one or more information bits of the plurality of information bits and one or more check bits, and all information bits in the plurality of first component codewords and the plurality of second component codewords constitute an information bit matrix; and

each second encoding sub-block includes a first check matrix; the first check matrix includes a plurality of first check bit sets each including one or more check bits, a first check bit set is determined based on bits of a first bit matrix with same side lengths, and the first check bit set and the bits of the first bit matrix constitute a third component codeword; and

wherein the first bit matrix includes any one of: part or all of information bits of the plurality of information bits, part or all of check bits in the plurality of first component codewords, or part or all of check bits in the plurality of second component codewords.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2024
From: PAN, CHUNPO
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 068208/0386 →
Continuity (2)
Provisional Application 63624608 · Jan 24, 2024
Related Publication 20250240034A1 · Jul 24, 2025
References Cited (9)
US 11683125B2 · Ye · 2023 [cited by examiner]
US 20090158112A1 · Oh et al. · 2009 [cited by applicant]
US 20200136650A1 · Huang · 2020 [cited by examiner]
US 20210111737A1 · Shin · 2021 [cited by examiner]
WO 2014117836A1 · 2014 [cited by applicant]
WO 2017178264A1 · 2017 [cited by applicant]
Cideciyan et al., “Product Codes for Data Storage on Magnetic Tape,” IEEE Transactions on Magnetics, vol. 53, No. 2, Feb. 2017, 10 pages. [cited by applicant]
Thomas Mittelholzer, “Performance Analysis of Iteratively Decoded 3-Dimensional Product Codes,” 2018 IEEE International Symposium on Information Theory (ISIT), doi: 10.1109/ISIT.2018.8437938, Jun. 17-22, 2018, 5 pages. [cited by applicant]
Shehadeh et al., “Generalized Staircase Codes with Arbitrary Bit Degree,” Optical Fiber Communication Conference (OFC) 2024, Technical Digest Series, Feb. 2024, paper W4C.2, https://opg.optica.org/abstract.cfm?URI=OFC-2… [cited by applicant]