Semiconductor structure with front side source drain contact and oppositely positioned source drain contacts
Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures over a substrate, and a gate structure surrounding the nanostructures. The gate structure includes gate dielectric layers and gate electrode layers. The semiconductor structure also includes a source/drain (S/D) structure adjacent to the gate structure, and an inner spacer layer between the gate structure and the S/D structure. The semiconductor structure further includes a filling layer over the gate structure, and the filling layer has a protrusion portion embedded in a space, the space is surrounded by the inner spacer, the gate dielectric layer and the gate electrode layer. The semiconductor structure also includes a first S/D contact structure formed over the filling layer.
1 . A semiconductor structure, comprising:
nanostructures over a substrate;
a gate structure surrounding the nanostructures, wherein the gate structure comprises gate dielectric layers and gate electrode layers;
a source/drain (S/D) structure adjacent to the gate structure;
a first S/D contact structure formed over a back side of the S/D structure;
a first layer formed on a topmost gate electrode layer and adjacent to the first S/D contact structure, wherein a topmost surface of the gate dielectric layer is lower than a topmost surface of the gate electrode layer filling; and
a second S/D contact structure formed over a front side of the S/D structure, wherein the first S/D contact structure and the second S/D contact structure are on opposite sides of the S/D structure.
2 . The semiconductor structure as claimed in claim 1 ,
wherein the second S/D contact structure is electrically connected to the first S/D contact structure by the S/D structure.
3 . The semiconductor structure as claimed in claim 1 , further comprising:
an air gap formed in the first layer.
4 . The semiconductor structure as claimed in claim 1 , further comprising:
an inner spacer between the gate structure and the S/D structure, wherein the inner spacer is in direct contact with the first layer.
5 . The semiconductor structure as claimed in claim 1 , further comprising:
a silicide layer between the first S/D contact structure and the S/D structure, wherein a top surface of the silicide layer is lower than a top surface of the first layer.
6 . The semiconductor structure as claimed in claim 1 , further comprising:
a dielectric layer between the first layer and the S/D structure, wherein the dielectric layer is in direct contact with the first layer.
7 . The semiconductor structure as claimed in claim 1 , wherein the first S/D contact structure is in direct contact with the first layer.
8 . The semiconductor structure as claimed in claim 1 , wherein the first S/D contact structure comprises a first liner layer and a first conductive layer.
9 . The semiconductor structure as claimed in claim 1 , wherein an interface between the first layer and the gate dielectric layer is lower than the topmost surface of the gate electrode layer.
10 . A semiconductor structure, comprising:
nanostructures over a substrate;
a gate structure surrounding the nanostructures, wherein the gate structure comprises gate dielectric layers and gate electrode layers;
a source/drain (S/D) structure adjacent to the gate structure;
an inner spacer layer between the gate structure and the S/D structure;
a first layer over the gate structure, wherein the first layer has a protrusion portion embedded in a space, the space is surrounded by the inner spacer layer, the gate dielectric layer and the gate electrode layer; and
a first S/D contact structure formed over the first layer, wherein the first layer is closer to a back side of the S/D structure than a front side of the S/D structure.
11 . The semiconductor structure as claimed in claim 10 , wherein the first layer and the gate dielectric layer are made of different materials.
12 . The semiconductor structure as claimed in claim 10 , wherein an interface between the first layer and the gate dielectric layer is lower than a topmost surface of the gate electrode layer.
13 . The semiconductor structure as claimed in claim 10 , further comprising:
a second S/D contact structure formed over a second side of the S/D structure, wherein the second S/D contact structure is electrically connected to the first S/D contact structure by the S/D structure.
14 . The semiconductor structure as claimed in claim 10 , further comprising:
an air gap between the first layer and one of the gate dielectric layers.
15 . The semiconductor structure as claimed in claim 10 , further comprising:
a dielectric layer between the first layer and the S/D structure, wherein the dielectric layer is in direct contact with the first layer.
16 . The semiconductor structure as claimed in claim 10 , wherein the gate electrode layer is isolated from the first S/D contact structure by the first layer.
17 . A semiconductor structure, comprising:
nanostructures over a substrate;
a gate structure surrounding the nanostructures, wherein the gate structure comprises gate dielectric layers and gate electrode layers;
a source/drain (S/D) structure adjacent to the gate structure;
an inner spacer layer between the gate structure and the S/D structure;
a first layer over the gate structure, wherein the first layer has a vertical portion and horizontal portion, and the vertical portion is between the inner spacer layer and the gate electrode layer; and
a first S/D contact structure formed over the S/D structure, wherein the first layer is between the gate structure and the first S/D contact structure, and the horizontal portion of the first layer is closer to the first S/D contact structure than the vertical portion of layer.
18 . The semiconductor structure as claimed in claim 17 , further comprising:
a dielectric layer between the first layer and the S/D structure.
19 . The semiconductor structure as claimed in claim 17 , wherein a bottommost surface of the first layer is lower than a topmost surface of the inner spacer layer.
20 . The semiconductor structure as claimed in claim 17 , wherein the first layer covers a topmost surface of the inner spacer layer.