Integrated circuit structures having AOI gates with routing across nanowires
Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.
1 . An integrated circuit structure, comprising:
a stack of horizontal nanowires along a vertical direction; and
a gate stack over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in a gate electrode in the vertical direction, the one or more cuts vertically between adjacent nanowires of the stack of horizontal nanowires.
2 . The integrated circuit structure of claim 1 , further comprising:
a conductive routing layer extending laterally between a pair of the horizontal nanowires.
3 . The integrated circuit structure of claim 1 , wherein the stack of horizontal nanowires comprises one or more nanowires of a first conductivity type above one or more wires of the second conductivity type.
4 . The integrated circuit structure of claim 1 , wherein the one or more nanowires of the first conductivity type are P-channel nanowires, and the one or more nanowires of the second conductivity type are N-channel nanowires.
5 . The integrated circuit structure of claim 1 , wherein the one or more cuts in the gate stack comprises a cut between all pairs of nanowires.
6 . An integrated circuit structure, comprising:
a stack of horizontal nanowires along a vertical direction;
a conductive contact laterally adjacent to a source or drain region of the stack of horizontal nanowires, the conductive contact having one or more cuts in the vertical direction; and
a gate stack over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in a gate electrode in the vertical direction, the one or more cuts vertically between adjacent nanowires of the stack of horizontal nanowires.
7 . The integrated circuit structure of claim 6 , further comprising:
a conductive routing layer extending laterally between a pair of the horizontal nanowires.
8 . The integrated circuit structure of claim 6 , wherein the stack of horizontal nanowires comprises one or more nanowires of a first conductivity type above one or more wires of the second conductivity type.
9 . The integrated circuit structure of claim 6 , wherein the one or more nanowires of the first conductivity type are P-channel nanowires, and the one or more nanowires of the second conductivity type are N-channel nanowires.
10 . The integrated circuit structure of claim 6 , wherein the gate stack is laterally spaced apart from the conductive contact.
11 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a stack of horizontal nanowires along a vertical direction; and
a gate stack over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in a gate electrode in the vertical direction, the one or more cuts vertically between adjacent nanowires of the stack of horizontal nanowires.
12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.
13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a stack of horizontal nanowires along a vertical direction;
a conductive contact laterally adjacent to a source or drain region of the stack of horizontal nanowires, the conductive contact having one or more cuts in the vertical direction; and
a gate stack over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in a gate electrode in the vertical direction, the one or more cuts vertically between adjacent nanowires of the stack of horizontal nanowires.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.