Multi-channel high electron mobility transistor with reduced input capacitance
A high-electron mobility transistor includes a semiconductor body including a plurality of type III-nitride semiconductor layers stacked on top of one another, thereby forming a plurality of two-dimensional first charge type gas channels and at least one two-dimensional second charge type gas channel vertically in between two of the two-dimensional first charge type gas channel, source and drain electrodes that are laterally spaced apart from one another and in ohmic contact with the plurality of two-dimensional first charge type gas channel, a gate structure configured to control a conductive connection between the source and drain electrodes by controlling a conductive state of the plurality of two-dimensional first charge type gas channels, and a charge dissipation structure that is configured to remove second charge type carriers from the two-dimensional second charge type gas channel during an off-state of the high-electron mobility transistor.
1 . A high-electron mobility transistor, comprising:
a semiconductor body comprising a plurality of type III-nitride semiconductor layers stacked on top of one another, thereby forming a plurality of two-dimensional first charge type gas channels and at least one two-dimensional second charge type gas channel vertically in between two of the two-dimensional first charge type gas channels,
source and drain electrodes that are laterally spaced apart from one another and in ohmic contact with the plurality of two-dimensional first charge type gas channel;
a gate structure configured to control a conductive connection between the source and drain electrodes by controlling a conductive state of the plurality of two-dimensional first charge type gas channels; and
a charge dissipation structure that is configured to remove second charge type carriers from the at least one two-dimensional second charge type gas channel during an off-state of the high-electron mobility transistor.
2 . The high-electron mobility transistor of claim 1 , wherein the charge dissipation structure comprises one or more regions of second conductivity type semiconductor material extending through the plurality of type III-nitride semiconductor layers and directly interfacing with the at least one two-dimensional second charge type gas channel.
3 . The high-electron mobility transistor of claim 2 , wherein the charge dissipation structure and the source electrode are connected to the same potential.
4 . The high-electron mobility transistor of claim 2 , wherein the gate structure comprises a plurality of gate columns, and wherein each of the gate columns is a region of second conductivity type semiconductor material that extends through the plurality of type III-nitride semiconductor layers and directly interfaces with the at least one two-dimensional second charge type gas channel.
5 . The high-electron mobility transistor of claim 4 , further comprising a barrier structure that is laterally in between the gate structure and an access region of the high-electron mobility transistor, wherein the barrier structure forms an energy barrier that prevents second charge type carriers from flowing between the access region of the high-electron mobility transistor and the gate structure.
6 . The high-electron mobility transistor of claim 5 , wherein the barrier structure is a region of first conductivity type semiconductor material that extends through the plurality of type III-nitride semiconductor layers and separates the access region of the high-electron mobility transistor from the gate structure.
7 . The high-electron mobility transistor of claim 5 , wherein the charge dissipation structure is disposed within the access region.
8 . The high-electron mobility transistor of claim 5 , wherein the charge dissipation structure comprises a plurality of charge dissipation columns, wherein each of the charge dissipation columns is a region of second conductivity type semiconductor material that extends through the plurality of type III-nitride semiconductor layers and directly interfaces with the at least one two-dimensional second charge type gas channel.
9 . The high-electron mobility transistor of claim 8 , wherein the charge dissipation columns and the gate columns differ from one another with respect to at least one of the following parameters:
dopant concentration;
lateral spacing in a second direction that is perpendicular to a current flow direction of the high-electron mobility transistor; and
total size.
10 . The high-electron mobility transistor of claim 9 , wherein the parameters of the charge dissipation columns and the gate columns are such that the plurality of two-dimensional first charge type gas channels in between the gate columns is fully depleted at zero gate-source voltage and the plurality of two-dimensional first charge type gas channels in between the charge dissipation columns is populated at zero gate-source voltage.
11 . The high-electron mobility transistor of claim 2 , wherein the gate structure comprises a gate electrode and an electrically insulating material or Schottky barrier between the at least one two-dimensional second charge type gas channel and the gate electrode.
12 . The high-electron mobility transistor of claim 11 , wherein the charge dissipation structure is at least partially overlapping with the source electrode.
13 . The high-electron mobility transistor of claim 12 , wherein the one or more regions of second conductivity type semiconductor material from the charge dissipation structure extend past the gate structure and towards the drain electrode.