Pixel circuit including transistor including terminal including polycrystalline silicon doped with impurity and display device including the pixel circuit
A pixel circuit includes a first transistor a first gate terminal electrically connected to a gate node, a first terminal including polycrystalline silicon doped with a first impurity and electrically connected to a first voltage and a second terminal including polycrystalline silicon doped with the first impurity, and a second transistor a second gate terminal electrically connected to a first gate signal, a third terminal including polycrystalline silicon doped with a second impurity and electrically connected to the gate node and a fourth terminal including polycrystalline silicon doped with the second impurity.
1 . A pixel circuit comprising:
a first transistor including:
a first gate terminal electrically connected to a gate node;
a first terminal including polycrystalline silicon doped with a first impurity and electrically connected to a first voltage; and
a second terminal including polycrystalline silicon doped with the first impurity;
a second transistor including:
a second gate terminal electrically connected to a first gate signal;
a third terminal including polycrystalline silicon doped with a second impurity different from the first impurity and electrically connected to the gate node; and
a fourth terminal including polycrystalline silicon doped with the second impurity; and
a light-emitting diode including:
an anode terminal electrically connected to the second terminal; and
a cathode terminal electrically connected to a second voltage,
wherein the anode terminal is further electrically connected to the fourth terminal.
2 . The pixel circuit of claim 1 , wherein the first impurity includes a P-type impurity, and the second impurity includes an N-type impurity.
3 . The pixel circuit of claim 1 , wherein the first transistor is a p-channel metal-oxide-semiconductor transistor, and the second transistor is an n-channel metal-oxide-semiconductor transistor.
4 . The pixel circuit of claim 1 , further comprising:
a storage capacitor including a first capacitor terminal electrically connected to the gate node and a second capacitor terminal electrically connected to an initialization voltage.
5 . The pixel circuit of claim 4 , further comprising:
a program capacitor including a third capacitor terminal electrically connected to a data voltage and a fourth capacitor terminal electrically connected to the anode terminal.
6 . The pixel circuit of claim 1 , further comprising:
a third transistor including a third gate terminal electrically connected to a second gate signal, a fifth terminal including polycrystalline silicon doped with the second impurity and electrically connected to the gate node and a sixth terminal including polycrystalline silicon doped with the second impurity.
7 . The pixel circuit of claim 1 , further comprising:
a third transistor including a third gate terminal electrically connected to a second gate signal, a fifth terminal including polycrystalline silicon doped with the first impurity and electrically connected to the gate node and a sixth terminal including polycrystalline silicon doped with the first impurity.
8 . A pixel circuit comprising:
a first transistor including:
a first gate terminal electrically connected to a gate node;
a first terminal including polycrystalline silicon doped with a first impurity and electrically connected to a first voltage; and
a second terminal including polycrystalline silicon doped with the first impurity;
a second transistor including:
a second gate terminal electrically connected to a first gate signal;
a third terminal including polycrystalline silicon doped with the first impurity and electrically connected to the gate node; and
a fourth terminal including polycrystalline silicon doped with the first impurity;
a third transistor including:
a third gate terminal electrically connected to a second gate signal;
a fifth terminal including polycrystalline silicon doped with a second impurity different from the first impurity and electrically connected to the gate node; and
a sixth terminal including polycrystalline silicon doped with the second impurity; and
a light-emitting diode including:
an anode terminal electrically connected to the second terminal; and
a cathode terminal electrically connected to a second voltage,
wherein the anode terminal is further electrically connected to the fourth terminal.
9 . The pixel circuit of claim 8 , wherein the first impurity includes a P-type impurity, and the second impurity includes an N-type impurity.
10 . The pixel circuit of claim 8 , wherein the first transistor is a p-channel metal-oxide-semiconductor transistor, and the second transistor is an n-channel metal-oxide-semiconductor transistor.