Device variation extraction chip
View Patent ↗The present application discloses a device variation extraction chip, including m MOS devices and one test key, where the test key has 2n pads; a drain of the (k(n−1)+i)-th MOS device is short-circuited with the i-th pad of the test key; a gate of the (k(n−1)+i)-th MOS device is short-circuited with the (n−1+i)-th pad of the test key; a source of each of the m MOS devices is short-circuited with the (2n−1)-th pad; a bulk of each of the m MOS devices is short-circuited with the 2n-th pad. The device variation extraction chip can save the chip area, save the test time, obtain a large amount of data, and improve the accuracy of the obtained device variation and device mismatch, without the addition of a photomask and process node steps.
1 . A device variation extraction chip, comprising m metal-oxide semiconductor (MOS) devices and one test key, wherein
the test key has 2n pads, n is an integer greater than 4, and m is an integer greater than n−1 and less than or equal to (n−1) 2 ;
a drain of the (k(n−1)+i) th MOS device is short-circuited with the i th pad of the test key, i is a positive integer less than or equal to n−1, and k is a natural number less than or equal to n−2;
a gate of the (k(n−1)+i) th MOS device is short-circuited with the (n−1+i) th pad of the test key;
a source of each of the m MOS devices is short-circuited with the (2n−1) th pad;
a bulk of each of the m MOS devices is short-circuited with the 2n th pad.
2 . The device variation extraction chip according to claim 1 , wherein
m
=
(
n
-
1
)
2
.
3 . The device variation extraction chip according to claim 1 , wherein m is 100, and n is 11;
a drain of the (10k+i) th MOS device is short-circuited with the i th pad of the test key, i is a positive integer less than or equal to 10, and k is a natural number less than or equal to 9;
a gate of the (10k+i) th h MOS device is short-circuited with the (10+1) th pad of the test key;
a source of each of the 100 MOS devices is short-circuited with the 21 st pad;
a bulk of each of the 100 MOS devices is short-circuited with the 22 nd pad.
4 . The device variation extraction chip according to claim 1 , wherein
m
<
(
n
-
1
)
2
.
5 . The device variation extraction chip according to claim 1 , wherein m is 54, and n is 9;
a drain of the (8k+i) th MOS device is short-circuited with the i th pad of the test key, i is a positive integer less than or equal to 8, and k is a natural number less than or equal to 7;
a gate of the (8k+i) th MOS device is short-circuited with the (8+i) th pad of the test key;
a source of each of the 54 MOS devices is short-circuited with the 17 th pad;
a bulk of each of the 54 MOS devices is short-circuited with the 18 th pad.