IP Library Granted Patent US 12,638,561
Granted Patent B2
US 12,638,561 · App. 18/169,723 · Granted May 26, 2026

Solid-state electronic scanning laser array with high-side and low-side switches for increased channels

Inventors: Angus Pacala (San Francisco, CA); Marvin Liu Shu (San Francisco, CA)
Assignee: Ouster, Inc.
G01S7/484G01S7/4817G01S17/10
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Quick Facts
Patent No.
US 12,638,561
App. No.
18/169,723
Granted
May 26, 2026
Kind
B2
Abstract

An electronically scanning emitter array that includes a two-dimensional array of light emitters arranged in k emitter banks. Each of the k emitter banks can include a subset of the light emitters in the two-dimensional array and can be independently operable to emit light from its subset of emitters. The electronically scanning emitter array can further include first and second capacitor banks coupled to provide energy to the two-dimensional array of light emitters and emitter array driving circuitry coupled to the first and second capacitor banks and to the k emitter banks. Each of the first and second capacitor banks can include at least one capacitor. The emitter array driving circuitry can include a first high-side switch coupled between the first capacitor bank and a voltage source, a second high-side switch coupled between the second capacitor bank and the voltage source, and k/2 low-side switches coupled between the k emitter banks and ground; and the emitter driving circuitry can be configured to fire one emitter bank in the k emitter banks at a time according to a firing sequence until each of the k emitter banks are fired.

Claims (42)

1 . An electronically scanning emitter array comprising:

a first high-side switch on a top side of a printed circuit board;

a first capacitor on the top side of the printed circuit board;

a first conductive rail coupled to the first capacitor and the first high-side switch and extending laterally through the printed circuit board;

a second high-side switch on a bottom side of the printed circuit board;

a second capacitor on a bottom side of the printed circuit board;

a second conductive rail coupled to the second capacitor and the second high-side switch and extending laterally through the printed circuit board;

an array of light emitters on the top side of the printed circuit board and comprising a first light emitter, a second light emitter, a third light emitter, and a fourth light emitter;

a first plurality of vertical interconnects coupled between the first conducive rail and the array of light emitters and coupling the first light emitter and the third light emitter to the first conductive rail;

a second plurality of vertical interconnects coupled between the second conducive rail and the array of light emitters and coupling the second light emitter and the fourth light emitter to the second conductive rail;

a plurality of low-side switches on the top side of the printed circuit board and coupled between one or more light emitters in the array of light emitters and ground and comprising a first low-side switch coupled to the first light emitter and the second light emitter and a second low-side switch coupled to the third light emitter and the fourth light emitter;

a first pull-down switch on the top side of the printed circuit board and coupled between the first conductive rail and ground; and

a second pull-down switch on the bottom side of the printed circuit board and coupled between the second conductive rail and ground.

2 . The electronically scanning emitter array of claim 1 wherein the printed circuit board comprises a ground plane extending laterally between the first conductive rail and the second conductive rail.

3 . The electronically scanning emitter array of claim 2 wherein the array of light emitters is formed as an integrated circuit.

4 . The electronically scanning emitter array of claim 3 further comprising a plurality of gate drivers on the top side of the printed circuit board and coupled to drive the plurality of low-side switches.

5 . The electronically scanning emitter array of claim 4 wherein each of the plurality of gate drivers is coupled to drive two of the plurality of low-side switches.

6 . The electronically scanning emitter array of claim 5 wherein the first plurality of vertical interconnects are coupled between the integrated circuit and a heat sink on the bottom side of the printed circuit board and the second plurality of vertical interconnects are coupled between the integrated circuit and the heat sink on the bottom side of the printed circuit board.

7 . The electronically scanning emitter array of claim 6 wherein the integrated circuit is positioned on a ceramic substrate.

8 . The electronically scanning emitter array of claim 7 wherein each of the first plurality of vertical interconnects is coupled to one or more columns of light emitters and each of the second plurality of vertical interconnects is coupled to one or more columns of light emitters, wherein the first plurality of vertical interconnects and the second plurality of vertical interconnects, along with their one or more columns of light emitters, are arranged in an interleaved manner.

9 . The electronically scanning emitter array of claim 8 wherein each low-side switch is coupled to a column of light emitters that is coupled to one of the first plurality of vertical interconnects and an adjacent column of light emitters that is coupled to one of the second plurality of vertical interconnects.

10 . An electronically scanning emitter array comprising:

a first high-side switch;

a first capacitor coupled to the first high-side switch;

a second high-side switch;

a second capacitor coupled to the second high-side switch;

a first plurality of columns of light emitters coupled to the first high-side switch and the first capacitor, the first plurality of columns of light emitters comprising a first column of light emitters and a third column of light emitters;

a second plurality of columns of light emitters coupled to the second high-side switch and the second capacitor, the second plurality of columns of light emitters comprising a second column of light emitters and a fourth column of light emitters;

a plurality of low-side switches, each low side switch coupled to at least one of the first plurality of columns of light emitters and at least one of the second plurality of columns of light emitters, the plurality of low-side switches comprising a first low-side switch coupled to the first column of light emitters and the second column of light emitters and a second low-side switch coupled to the third column of light emitters and the fourth column of light emitters;

a first pull-down switch coupled to the first high-side switch; and

a second pull-down switch coupled to the second high-side switch.

11 . The electronically scanning emitter array of claim 10 wherein each of the plurality of low-side switches is coupled to one of the first plurality of columns of light emitters and one of the second plurality of columns of light emitters.

12 . The electronically scanning emitter array of claim 10 wherein the first high-side switch is coupled between the first capacitor and a power supply terminal and the second high-side switch is coupled between the second capacitor and the power supply terminal.

13 . The electronically scanning emitter array of claim 10 further comprising a plurality of gate drivers coupled to drive the plurality of low-side switches, wherein each of the plurality of gate drivers is coupled to drive two of the plurality of low-side switches.

14 . The electronically scanning emitter array of claim 10 wherein each of the first plurality of columns of light emitters and each of the second plurality of columns of light emitters comprises an emitter in series with a protection diode.

15 . An electronically scanning emitter array comprising a control circuit to sequentially fire a first plurality of light emitters and then to sequentially fire a second plurality of light emitters, wherein the control circuit:

drives a first high-side switch coupled to the first plurality of light emitters, the first plurality of light emitters comprising a first light emitter and a third light emitter, and a second high-side switch coupled to the second plurality of light emitters, the second plurality of light emitters comprising a second light emitter and a fourth light emitter;

drives a plurality of low-side switches coupled to one of each of the first plurality of light emitters and the second plurality of light emitters, the plurality of low-side switches comprising a first low-side switch coupled to the first light emitter and the second light emitter and a second low-side switch coupled to the third light emitter and the fourth light emitter; and

drives a first pull-down switch coupled to the first high-side switch and a second pull-down switch coupled to the second high-side switch.

16 . The electronically scanning emitter array of claim 15 wherein the control circuit closes the first high-side switch to charge a first capacitor coupled to the first plurality of light emitters and the control circuit closes the second high-side switch to charge a second capacitor coupled to the second plurality of light emitters.

17 . The electronically scanning emitter array of claim 16 wherein the control circuit sequentially closes the plurality of low-side switches to fire the first plurality of light emitters, and then again sequentially closes the plurality of low-side switches to fire the second plurality of light emitters.

18 . The electronically scanning emitter array of claim 10 wherein the first low-side switch and the second low-side switch are further coupled directly to ground.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2023
From: PACALA, ANGUS; SHU, MARVIN LIU
To: OUSTER, INC.
Reel/Frame 063645/0379 →
Continuity (4)
Continuation 16696540 · Nov 26, 2019
Provisional Application 62828113 · Apr 2, 2019
Provisional Application 62784918 · Dec 26, 2018
Related Publication 20230305118A1 · Sep 28, 2023
References Cited (49)
US 7969558B2 · Hall · 2011 [cited by applicant]
US 8675181B2 · Hall · 2014 [cited by applicant]
US 8767190B2 · Hall · 2014 [cited by applicant]
US 9030836B2 · Park et al. · 2015 [cited by applicant]
US 9236705B2 · Deppe · 2016 [cited by applicant]
US 9245874B2 · Demuynck · 2016 [cited by examiner]
US 9551791B2 · Van Den Bossche et al. · 2017 [cited by applicant]
US 9992477B2 · Pacala et al. · 2018 [cited by applicant]
US 10063849B2 · Pacala et al. · 2018 [cited by applicant]
US 10444359B2 · Pacala et al. · 2019 [cited by applicant]
US 20070024840A1 · Fetzer et al. · 2007 [cited by applicant]
US 20150131080A1 · Retterath et al. · 2015 [cited by applicant]
US 20170343653A1 · Weinberg · 2017 [cited by applicant]
US 20180143324A1 · Keilaf et al. · 2018 [cited by applicant]
US 20180299554A1 · Van Dyck et al. · 2018 [cited by applicant]
US 20180301872A1 · Burroughs et al. · 2018 [cited by applicant]
US 20180301875A1 · Burroughs · 2018 [cited by examiner]
US 20180329062A1 · Pacala et al. · 2018 [cited by applicant]
US 20180329065A1 · Pacala et al. · 2018 [cited by applicant]
US 20190011561A1 · Pacala et al. · 2019 [cited by applicant]
US 20190011567A1 · Pacala et al. · 2019 [cited by applicant]
US 20190064355A1 · Pacala et al. · 2019 [cited by applicant]
US 20200178361A1 · Oka · 2020 [cited by examiner]
CN 104247566A · 2014 [cited by applicant]
CN 106725323A · 2017 [cited by applicant]
CN 108028507A · 2018 [cited by applicant]
CN 108603932A · 2018 [cited by applicant]
CN 108885263A · 2018 [cited by applicant]
CN 109073756A · 2018 [cited by applicant]
EP 3045935A1 · 2016 [cited by applicant]
EP 3316000A1 · 2018 [cited by applicant]
TW 201141320A · 2011 [cited by applicant]
WO 2017025958A1 · 2017 [cited by applicant]
WO 2018065426A1 · 2018 [cited by applicant]
WO 2018065427A1 · 2018 [cited by applicant]
WO 2018065428A2 · 2018 [cited by applicant]
WO 2018065429A1 · 2018 [cited by applicant]
WO 2018122415A1 · 2018 [cited by applicant]
WO 2018197441A1 · 2018 [cited by applicant]
CN201980092370.3, “Office Action”, Dec. 28, 2023, 24 pages. [cited by applicant]
U.S. Appl. No. 16/696,540, Notice of Allowance, Mailed On Sep. 21, 2022, 8 pages. [cited by applicant]
Application No. EP19906205.0, Extended European Search Report, Mailed On Jun. 20, 2022, 10 pages. [cited by applicant]
Application No. PCT/US2019/067667, International Preliminary Report on Patentability, Mailed On Jul. 8, 2021, 9 pages. [cited by applicant]
Application No. PCT/US2019/067667, International Search Report and Written Opinion, Mailed On Feb. 27, 2020, 10 pages. [cited by applicant]
KR10-2021-7023679, “Office Action”, Jul. 8, 2024, 7 pages. [cited by applicant]
CN201980092370.3, “Office Action”, Aug. 28, 2024, 14 pages. [cited by applicant]
KR10-2021-7023679, “Notice of Decision to Grant”, Mar. 4, 2025, 5 pages. [cited by applicant]
CN201980092370.3 , “Notice of Decision to Grant”, Mar. 24, 2025, 6 pages. [cited by applicant]
EP19906205.0, “Intention to Grant”, Apr. 23, 2025, 8 pages. [cited by applicant]