Memory device, memory system, and program operation method thereof
A memory device includes a memory cell array and peripheral circuits coupled to the memory cell array. The peripheral circuits are configured to perform twice program operations on one or more first memory cells in the memory cell array for storing cold data into the one or more first memory cells. The twice program operations include a first time program operation and a second time program operation. To perform the twice program operations, the peripheral circuits are configured to performing the first time program operation for successfully storing the cold data into the one or more first memory cells, and performing the second time program operation for improving retention characteristics of the cold data.
1 . A memory device, comprising:
a memory cell array; and
peripheral circuits coupled to the memory cell array and configured to:
perform twice program operations on one or more first memory cells in the memory cell array for storing cold data into the one or more first memory cells, the twice program operations comprising a first time program operation and a second time program operation, wherein performing the twice program operations comprises:
performing the first time program operation for successfully storing the cold data into the one or more first memory cells; and
in response to determining that the first time program operation on the one or more first memory cells is successful, performing the second time program operation for storing the cold data into the one or more first memory cells, the second time program operation being configured to narrow a threshold voltage distribution, corresponding to a programmed state among the one or more first memory cells, for improving retention characteristics of the cold data.
2 . The memory device of claim 1 , wherein:
the peripheral circuits are further configured to perform once program operation on one or more second memory cells in the memory cell array for storing hot data into the one or more second memory cells; and
the cold data stored in the one or more first memory cells has retention characteristics better than the hot data stored in the one or more second memory cells.
3 . The memory device of claim 2 , wherein the peripheral circuits are configured to:
apply a programming voltage to a word line corresponding to the one or more first memory cells, and a pass voltage to another word line corresponding to the one or more second memory cells to perform the first time program operation on the one or more first memory cells.
4 . The memory device of claim 2 , wherein an access frequency of the cold data is less than an access frequency of the hot data, and the access frequency of the cold data is less than or equal to a threshold frequency.
5 . The memory device of claim 1 , wherein the first time program operation is substantially identical to the second time program operation.
6 . The memory device of claim 1 , wherein after the second time program operation, the one or more first memory cells are programmed into different states, and a threshold voltage range of a same programmed state after the second time program operation is narrower than after the first time program operation.
7 . The memory device of claim 1 , wherein a first target programming state achieved by the first time program operation on the one or more first memory cells is substantially identical to a second target programming state achieved by the second time program operation on the one or more first memory cells.
8 . The memory device of claim 1 , wherein:
the first time program operation comprises a first programming pulse that includes a first initial pulse voltage and a first initial pulse duration, and the second time program operation comprises a second programming pulse that includes a second initial pulse voltage and a second initial pulse duration; and
at least one of the first initial pulse voltage being substantially identical to the second initial pulse voltage or the first initial pulse duration being substantially identical to the second initial pulse duration is satisfied.
9 . The memory device of claim 8 , wherein:
the first time program operation comprises a first pulse voltage based on a first initial pulse voltage increment a first incremental voltage, and the second time program operation comprises a second pulse voltage based on a second initial pulse voltage increment a second incremental voltage; and
the first incremental voltage is substantially identical to the second incremental voltage.
10 . The memory device of claim 1 , wherein the peripheral circuits are configured to:
perform the first time program operation on the one or more first memory cells and the first time program operation on one or more second memory cells sequentially.
11 . A memory system, comprising:
a memory controller coupled to a memory device and configured to send one or more first instructions corresponding to cold data, the memory device comprising a memory cell array and peripheral circuits coupled to the memory cell array,
wherein:
the peripheral circuits are configured to perform twice program operations, in response to the one or more first instructions, on one or more first memory cells in the memory cell array for storing the cold data into the one or more first memory cells, the twice program operations comprising a first time program operation and a second time program operation; and
the twice program operations comprise:
perform the first time program operation for successfully storing the cold data into the one or more first memory cells; and
upon determining that the first time program operation has been successfully performed on the one or more first memory cells, perform the second time program operation for storing the cold data into the one or more first memory cells, the second time program operation being configured to narrow a threshold voltage distribution, corresponding to a programmed state among the one or more first memory cells, for improving retention characteristics of the cold data.
12 . The memory system of claim 11 , wherein after the second time program operation, the first memory cells are programmed into different states, and a threshold voltage range of a same programmed state after the second time program operation is narrower than after the first time program operation.
13 . The memory system of claim 11 , wherein:
the first time program operation is substantially identical to the second time program operation; and
a first target programming state achieved by the first time program operation on the one or more first memory cells is substantially identical to a second target programming state achieved by the second time program operation on the one or more first memory cells.
14 . A memory system, comprising:
a memory controller coupled to a memory device, and configured to send one or more first instructions corresponding to cold data, and one or more second instructions corresponding to hot data; and
the memory device comprising a memory cell array and peripheral circuits coupled to the memory cell array,
wherein the peripheral circuits are configured to:
perform twice program operations, in response to the one or more first instructions, on one or more first memory cells in the memory cell array for storing the cold data into the one or more first memory cells, the twice program operations comprising a first time program operation and a second time program operation, the second time program operation being performed using the cold data on the one or more first memory cells upon a determination of a successful result of the first time program operation for storing the cold data into the one or more first memory cells; and
perform once program operation, in response to the one or more second instructions, on one or more second memory cells in the memory cell array for storing hot data into the one or more second memory cells.
15 . The memory system of claim 14 , wherein:
the peripheral circuits are further configured to perform once program operation on the one or more second memory cells in the memory cell array for storing the hot data into the one or more second memory cells; and
the cold data stored in the one or more first memory cells has retention characteristics better than the hot data stored in one or more second memory cells.
16 . The memory system of claim 14 , wherein the first time program operation is substantially identical to the second time program operation.
17 . The memory system of claim 14 , wherein an access frequency of the cold data is less than an access frequency of the hot data, and the access frequency of the cold data is less than or equal to a threshold frequency.
18 . A method for programming data, comprising:
performing twice program operations on one or more first memory cells in a memory cell array for storing cold data into the one or more first memory cells, the twice program operations comprising a first time program operation and a second time program operation,
wherein performing the twice program operations comprises:
performing the first time program operation for successfully storing the cold data into the one or more first memory cells; and
performing the second time program operation for improving retention characteristics of the cold data, wherein:
the first time program operation comprises a first programming pulse that includes a first initial pulse voltage and a first initial pulse duration, and the second time program operation comprises a second programming pulse that includes a second initial pulse voltage and a second initial pulse duration; and
at least one of the first initial pulse voltage being substantially identical to the second initial pulse voltage or the first initial pulse duration being substantially identical to the second initial pulse duration is satisfied.
19 . The method of claim 18 , further comprising:
performing once program operation on one or more second memory cells in the memory cell array for storing hot data into the one or more second memory cells,
wherein the cold data stored in the one or more first memory cells has retention characteristics better than the hot data stored in the one or more second memory cells.
20 . The method of claim 18 , wherein the first time program operation is substantially identical to the second time program operation.