Available memory optimization to manage multiple memory channels
Systems, apparatuses, and methods may provide for optimizing the available memory in a power conscious compute platform. For example, a semiconductor apparatus includes logic to communicate with a system memory to divide a plurality of memory channels into functional channels and performance channels. The functional channels are in an active power state during a boot process and the performance channels are in an idle power state during the boot process. The semiconductor apparatus includes logic to track memory usage and bring the performance channels out of the idle power state and into the active power state in response to the tracked memory usage.
1 . A semiconductor apparatus comprising:
a substrate on which to mount memory chips, the memory chips organized as a plurality of memory channels, including a functional channel having a first memory range always available to an operating system (OS) and a performance channel having a second memory range selectively available to the OS based on usage of the memory chips; and
circuitry coupled to the substrate, wherein the circuitry is configured to:
track memory usage for the memory chips, wherein the functional channel is in an active power state during a boot process and the performance channel is in an idle power state during the boot process; and
selectively bring the performance channel out of the idle power state and into the active power state in response to an increase in memory usage and selectively put the performance channel into the idle power state and out of the active power state in response to a decrease in memory usage.
2 . The semiconductor apparatus of claim 1 , wherein the circuitry is further configured to:
divide the plurality of memory channels into the functional channel and the performance channel; and
train the plurality of memory channels to function as either the functional channel or as the performance channel in response to powering on.
3 . The semiconductor apparatus of claim 1 ,
wherein the performance channel is not available to the OS and does not retain data when in the idle power state, and
wherein the performance channel is available to the OS and retains data when in the active power state.
4 . The semiconductor apparatus of claim 1 , wherein the circuitry is further configured to:
predict future memory demand based on tracked memory usage; and
selectively bring the performance channel out of the idle power state and into the active power state in response to a predicted future increase in memory demand and selectively put the performance channel into the idle power state and out of the active power state in response to a predicted decrease in memory demand.
5 . The semiconductor apparatus of claim 1 , wherein the circuitry is further configured to:
move data from the performance channel either to storage or to the functional channel prior to bringing the performance channel out of the active power state and into the idle power state; and
remove availability of the OS to the performance channel prior to bringing the performance channel out of the active power state and into the idle power state.
6 . The semiconductor apparatus of claim 1 , wherein the semiconductor apparatus manages a system memory communicatively coupled to a processor.
7 . A non-transitory computer readable storage medium comprising executable program instructions stored thereon, which when executed by a computing system, cause the computing system to:
track memory usage for memory chips organized as a plurality of memory channels, including a functional channel having a first memory range always available to an operating system (OS) and a performance channel having a second memory range selectively available to the OS based on usage of the memory chips, wherein the functional channel is in an active power state during a boot process and the performance channel is in an idle power state during the boot process; and
selectively bring the performance channel out of the idle power state and into the active power state in response to an increase in memory usage and selectively put the performance channel into the idle power state and out of the active power state in response to a decrease in memory usage.
8 . The non-transitory computer readable storage medium of claim 7 , wherein the instructions, when executed, further cause the computing system to:
divide the plurality of memory channels into the functional channel and the performance channel; and
train the plurality of memory channels to function as either the functional channel or as the performance channel in response to powering on.
9 . The non-transitory computer readable storage medium of claim 7 ,:
wherein the performance channel is not available to the OS and does not retain data when in the idle power state, and
wherein the performance channel is available to the OS and retains data when in the active power state.
10 . The non-transitory computer readable storage medium of claim 7 , wherein the instructions, when executed, further cause the computing system to:
move data from the performance channel either to storage or to the functional channel prior to bringing the performance channel out of the active power state and into the idle power state; and
remove availability of the OS to the performance channel prior to bringing the performance channel out of the active power state and into the idle power state.
11 . The non-transitory computer readable storage medium of claim 7 , wherein the instructions, when executed, further cause the computing system to:
predict future memory demand based on tracked memory usage;
selectively bring the performance channel out of the idle power state and into the active power state in response to a predicted future increase in memory demand; and
selectively put the performance channel into the idle power state and out of the active power state in response to a predicted future decrease in memory demand.
12 . A method comprising:
tracking memory usage for memory chips organized as a plurality of memory channels, including a functional channel having a first memory range always available to an operating system (OS) and a performance channel having a second memory range selectively available to the OS based on usage of the memory chips, wherein the functional channel is in an active power state during a boot process and the performance channel is in an idle power state during the boot process; and
selectively bringing the performance channel out of the idle power state and into the active power state in response to an increase in memory usage and selectively putting the performance channel into the idle power state and out of the active power state in response to a decrease in memory usage.
13 . The method of claim 12 , further comprising:
dividing the plurality of memory channels into the functional channel and the performance channel; and
training the plurality of memory channels to function as either the functional channel or as the performance channel in response to powering on.
14 . The method of claim 12 ,
wherein the performance channel is not available to the OS and does not retain data when in the idle power state, and
wherein the performance channel is available to the OS and retains data when in the active power state.
15 . The method of claim 12 , further comprising:
moving data from the performance channel either to storage or to the functional channel prior to bringing the performance channel out of the active power state and into the idle power state; and
removing availability of the OS to the performance channel prior to bringing the performance channel out of the active power state and into the idle power state.
16 . The method of claim 12 , further comprising:
predicting future memory demand based on tracked memory usage;
selectively bringing the performance channel out of the idle power state and into the active power state in response to a predicted future increase in memory demand; and
selectively putting the performance channel into the idle power state and out of the active power state in response to a predicted future decrease in memory demand.