DMA device, operating method thereof, and electronic device including DMA device
A direct memory access (DMA) device includes a controller, a read request issuing circuit, a read buffer temporarily storing read data and an arrival time of the read data, and a read buffer managing circuit that calculates an average bus latency and an average buffer residence time. The read request issuing circuit adjusts the issuing capability based on the average bus latency and the average buffer residence time. The DMA device operates by issuing a read request based on an issuing capability, storing an issuing time of the read request, receiving read data corresponding to the read request, temporarily storing the read data and an arrival time of the read data in a read buffer, calculating an average bus latency based on the issuing time of the read request, calculating an average buffer residence time, adjusting the issuing capability, and issuing the read request based on the adjusted issuing capability.
1 . A direct memory access (DMA) device that reads data utilized for an operation of an accelerator from a memory device, the DMA device comprising:
a controller configured to control an operation of the DMA device;
a read request issuing circuit configured to issue a read request based on an issuing capability and store an issuing time of the read request;
a read buffer configured to temporarily store read data corresponding to the read request and store an arrival time of the read data; and
a read buffer managing circuit configured to count a current time, calculate an average bus latency based on the issuing time of the read request when receiving the read data from the memory device, and calculate an average buffer residence time based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator,
wherein the read request issuing circuit is configured to adjust the issuing capability based on the average bus latency and the average buffer residence time and issue the read request based on the adjusted issuing capability.
2 . The DMA device of claim 1 , wherein the controller is configured to set an initial value of the issuing capability based on a size of the read buffer.
3 . The DMA device of claim 1 , wherein the read request issuing circuit comprises:
a request table configured to store the issued read request; and
an issuing time table configured to receive the current time from the read buffer managing circuit when the read request is issued, and store the received current time as the issuing time of the read request.
4 . The DMA device of claim 1 , wherein the read buffer comprises:
a read data buffer configured to temporarily store the read data; and
an arrival time table configured to receive the current time from the read buffer managing circuit when receiving the read data, and store the received current time as the arrival time of the read data.
5 . The DMA device of claim 4 , wherein the arrival time corresponds to a plurality of pieces of read data received according to a same read request.
6 . The DMA device of claim 1 , wherein,
when receiving the read data from the memory device, the read buffer is configured to transmit an arrival notice of the read data to the read request issuing circuit, and
when receiving the arrival notice of the read data, the read request issuing circuit is configured to output the issuing time of the read request corresponding to the read data to the read buffer managing circuit.
7 . The DMA device of claim 6 , wherein, when receiving the issuing time of the read request, the read buffer managing circuit is configured to calculate the average bus latency based on a difference between the issuing time of the read request and the current time.
8 . The DMA device of claim 1 , wherein, when the temporarily stored read data is output to the accelerator, the read buffer is configured to output the arrival time of the read data corresponding to the read data to the read buffer managing circuit.
9 . The DMA device of claim 8 , wherein, when receiving the arrival time of the read data, the read buffer managing circuit is configured to calculate the average buffer residence time based on a difference between the arrival time of the read data and the current time.
10 . The DMA device of claim 1 , wherein the read request issuing circuit is configured to adjust the issuing capability based on the average bus latency and the average buffer residence time at each of a plurality of preset adjustment time intervals.
11 . The DMA device of claim 1 , wherein the read request issuing circuit is configured to adjust the issuing capability in proportion to the average bus latency and adjust the issuing capability in inverse proportion to the average buffer residence time.
12 . The DMA device of claim 11 , wherein the read request issuing circuit is configured to adjust a number of pieces of data that is read from the memory device according to the read request in proportion to the issuing capability.
13 . An operating method of a direct memory access (DMA) device that reads data utilized for an operation of an accelerator from a memory device, the operating method comprising:
issuing, by a read request issuing circuit, a read request based on an issuing capability;
storing an issuing time of the read request in the read request issuing circuit;
receiving, by a read buffer, read data corresponding to the read request;
temporarily storing the read data corresponding to the read request in a read buffer;
storing an arrival time of the read data in the read buffer;
calculating, by a read buffer managing circuit, an average bus latency based on the issuing time of the read request;
calculating, by the read buffer managing circuit, an average buffer residence time based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator;
adjusting, by the read request issuing circuit, the issuing capability based on the average bus latency and the average buffer residence time; and
issuing, by the read request issuing circuit, the read request based on the adjusted issuing capability.
14 . The operating method of claim 13 , further comprising:
transmitting, by the read buffer, an arrival notice of the read data to the read request issuing circuit after receiving the read data; and
outputting, by the read request issuing circuit, the issuing time of the read request corresponding to the read data to the read buffer managing circuit when receiving the arrival notice of the read data.
15 . The operating method of claim 14 , wherein calculating the average bus latency comprises calculating the average bus latency based on a difference between the issuing time of the read request and a current time when receiving the issuing time of the read request.
16 . The operating method of claim 13 , further comprising:
outputting, by the read buffer, the arrival time of the read data corresponding to the read request to the read buffer managing circuit when the temporarily stored read data is output to the accelerator.
17 . The operating method of claim 16 , wherein calculating the average buffer residence time comprises calculating the average buffer residence time based on a difference between the arrival time of the read data and a current time when receiving the arrival time of the read data.
18 . The operating method of claim 13 , wherein adjusting the issuing capability comprises:
adjusting the issuing capability in proportion to the average bus latency; and
adjusting the issuing capability in inverse proportion to the average buffer residence time.
19 . The operating method of claim 18 , wherein issuing the read request comprises issuing the read request by adjusting a number of pieces of data that is read from the memory device according to the read request, in proportion to the issuing capability.
20 . An electronic device, comprising:
a memory device configured to store data;
an accelerator configured to operate based on the data stored in the memory device; and
a direct memory access (DMA) device configured to read data utilized for an operation of the accelerator from the memory device,
wherein the DMA device comprises:
a controller configured to control an operation of the DMA device;
a read request issuing circuit configured to issue a read request based on an issuing capability and store an issuing time of the read request;
a read buffer configured to temporarily store read data corresponding to the read request and store an arrival time of the read data; and
a read buffer managing circuit configured to count a current time, calculate an average bus latency based on the issuing time of the read request when receiving the read data from the memory device, and calculate an average buffer residence time based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator,
wherein the read request issuing circuit is configured to adjust the issuing capability based on the average bus latency and the average buffer residence time and issues the read request based on the adjusted issuing capability.