Chip control
A system, circuit, and method are described, among other things. An illustrative system is disclosed to include a processor and a memory storing data for processing by the processor. The data, when processed, causes the processor to receive an initiator message comprising a request to access one or more registers of a plurality of registers, determine that the initiator message corresponds to an entry of a privilege access table, determine a configured level of access control for the initiator message to access the one or more requested registers based at least in part on a group mapping table, and provide a level of access to the one or more requested registers corresponding to the received initiator message based on the initiator message corresponding to the entry of the privilege access table and based, at least in part, on the determined configured level of access control.
1 . A system for providing access in a control register fabric, comprising:
a processor; and
a memory storing data for processing by the processor, the data, when processed, causes the processor to:
receive an initiator message comprising a request to access one or more registers of a plurality of registers;
determine, from an entry of a privilege access table, an address range of the plurality of registers that are accessible by the initiator message;
determine, from a group mapping table that maps groups of registers to different functions, a privilege level for the initiator message; and
provide, for the initiator message, a level of access to the one or more requested registers based on the determined address range and the determined privilege level.
2 . The system of claim 1 , wherein the privilege access table comprises a plurality of entries, each entry comprising an index number, a source identification mask, a privilege level mask, a starting address, an ending address, a respective privilege level, or a combination thereof.
3 . The system of claim 2 , wherein the data stored in the memory, when processed, causes the processor to:
determine whether a source identification field in the initiator message matches a source identification mask of an entry in the privilege access table, a privilege level field in the initiator message matches a privilege level mask of the entry, and an address field in the initiator message is between a starting address and an ending address of the entry.
4 . The system of claim 1 , wherein the privilege access table comprises a plurality of entries ordered according to a priority order as indicated by an index number for each entry, and wherein the data stored in the memory, when processed, causes the processor to:
identify a first occurring entry match in the privilege access table according to the priority order.
5 . The system of claim 3 , wherein the group mapping table comprises a set of privilege level masks defined per function, and wherein each privilege level mask corresponds to a respective privilege level.
6 . The system of claim 5 , wherein the data stored in the memory, when processed, causes the processor to:
determine the privilege level from the set of privilege level masks based at least in part on a source identification field in the initiator message, a privilege level field in the initiator message, a read/write command field in the initiator message, or a combination thereof.
7 . The system of claim 1 , wherein the memory stores further data for processing by the processor that, when processed, causes the processor to:
generate a register transaction based at least in part on receiving the initiator message, wherein the register transaction comprises an indication of an instruction pointer register corresponding to the one or more requested registers, the instruction pointer register being determined based at least in part on an address of the one or more requested registers included within the initiator message.
8 . The system of claim 7 , wherein the address of the one or more requested registers comprises a same instruction pointer register that the initiator message is received within.
9 . The system of claim 7 , wherein the address of the one or more requested registers comprises a different instruction pointer register than the initiator message is received within.
10 . The system of claim 1 , wherein the memory stores further data for processing by the processor that, when processed, causes the processor to:
convert a register transaction to a control register transaction based at least in part on the initiator message comprising a different architecture than a control register architecture.
11 . The system of claim 1 , wherein the memory stores further data for processing by the processor that, when processed, causes the processor to:
generate a post transaction control logic for the initiator message based at least in part on determining whether the initiator message corresponds to an entry of the privilege access table, wherein the post transaction control logic comprises an indication of which registers of the plurality of registers are accessible by the initiator message.
12 . The system of claim 11 , wherein the post transaction control logic provides the level of access to the one or more requested registers corresponding to the received initiator message.
13 . The system of claim 1 , wherein the level of access enables read/write privileges within the one or more requested registers for the received initiator message.
14 . A circuit, comprising:
a control register switch comprising external switching logic, a transaction control logic block, and internal switching logic;
a processor; and
a memory storing data for processing by the processor, the data, when processed, causes the processor to:
receive an initiator message comprising a request to access one or more registers of a plurality of registers;
determine, from an entry of a privilege access table, an address range of the plurality of registers that are accessible by the initiator message;
determine, from a group mapping table that maps groups of registers to different functions, a privilege level of for the initiator message; and
provide, for the initiator message, a level of access to the one or more requested registers based on the determined address range and the determined privilege level.
15 . The circuit of claim 14 , wherein the privilege access table comprises a plurality of entries, each entry comprising an index number, a source identification mask, a privilege level mask, a starting address, an ending address, a respective level of access control, or a combination thereof.
16 . The circuit of claim 15 , wherein the data stored in the memory, when processed, causes the processor to:
determine whether a source identification field in the initiator message matches a source identification mask of an entry in the privilege access table, a privilege level field in the initiator message matches a privilege level mask of the entry, and an address field in the initiator message is between a starting address and an ending address of the entry, wherein the level of access control for the initiator message to access the one or more requested registers comprises a corresponding level of access control for the entry in the privilege access table.
17 . The circuit of claim 16 , wherein the group mapping table comprises a set of privilege level masks defined per function, and wherein each privilege level mask corresponds to a respective privilege level.
18 . The circuit of claim 17 , wherein the data stored in the memory, when processed, causes the processor to:
determine the privilege level based at least in part on a source identification field in the initiator message, a privilege level field in the initiator message, a read/write command field in the initiator message, or a combination thereof.
19 . The circuit of claim 14 , wherein the memory stores further data for processing by the processor that, when processed, causes the processor to:
generate, via the external switching logic, a register transaction based at least in part on receiving the initiator message, wherein the register transaction comprises an indication of an instruction pointer register corresponding to the one or more requested registers, the instruction pointer register being determined based at least in part on an address of the one or more requested registers included within the initiator message.
20 . A method for providing access in a control register fabric, comprising:
receiving an initiator message comprising a request to access one or more registers of a plurality of registers;
determining, from an entry of a privilege access table, an address range of the plurality of registers that are accessible by the initiator message;
determining, from a group mapping table that maps groups of registers to different functions, a privilege level for the initiator message; and
providing, for the initiator message, a level of access to the one or more requested registers based on the determined address range and the determined privilege level.