IP Library › Granted Patent US 12,639,559
Granted Patent B2
US 12,639,559 · App. 17/724,415 · Granted May 26, 2026

Calibration of electrical parameters in a deep learning artificial neural network

Inventor: Hieu Van Tran (San Jose, CA)
Assignee: Silicon Storage Technology, Inc.
G06N3/063G06N3/065G06N3/0442G06N3/0464G06N3/048G06N3/09G11C11/54G11C16/0425G11C29/028
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,639,559
App. No.
17/724,415
Granted
May 26, 2026
Kind
B2
Abstract

Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a method comprises adjusting a bias voltage applied to one or more non-volatile memory cells in an artificial neural network, performing a performance target check on the one or more non-volatile memory cells in the artificial neural network, and repeating the adjusting and performing until the performance target check indicates an electrical parameter is within a predetermined range.

Claims (16)

1 . A method comprising:

adjusting a bias voltage applied to one or more non-volatile memory cells in an artificial neural network;

performing a performance target check on the one or more non-volatile memory cells in the artificial neural network; and

repeating the adjusting and performing until the performance target check indicates an electrical parameter is within a predetermined range, wherein the electrical parameter is a neuron current or an averaged neuron current.

2 . The method of claim 1 , wherein the electrical parameter is a neuron current.

3 . The method of claim 1 , wherein the electrical parameter is an averaged neuron current.

4 . A system comprising:

a bias control circuit;

an array providing a sampled neuron current; and

a current source coupled to the array;

wherein a control gate bias or erase gate bias applied to the array is adjusted by the bias control circuit until the sampled neuron current is equal to current of the current source.

5 . A system comprising:

a bias control circuit;

an array providing a sampled neuron current; and

a resistor comprising a first terminal coupled to the array at a node and a second terminal coupled to ground;

wherein a control gate bias or erase gate bias applied to the array is adjusted by the bias control circuit until a voltage at the node equals a reference voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2022
From: TRAN, HIEU VAN
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 059642/0684 →
Continuity (2)
Provisional Application 63307983 · Feb 8, 2022
Related Publication 20230306246A1 · Sep 28, 2023
References Cited (26)
US 5029130A · Yeh · 1991 [cited by applicant]
US 6091632A · Yoshimi · 2000 [cited by examiner]
US 6292398B1 · Pasotti · 2001 [cited by examiner]
US 6747310B2 · Fan · 2004 [cited by applicant]
US 10748630B2 · Tran et al. · 2020 [cited by applicant]
US 20140006689A1 · Hashimoto · 2014 [cited by examiner]
US 20150270009A1 · Lee · 2015 [cited by examiner]
US 20170337466A1 · Bayat et al. · 2017 [cited by applicant]
US 20200150923A1 · Muralimanohar · 2020 [cited by applicant]
US 20200258942A1 · Leobandung · 2020 [cited by applicant]
US 20210175893A1 · Danial · 2021 [cited by applicant]
US 20230153585A1 · Mirhassani · 2023 [cited by examiner]
JP 2008159185A · 2008 [cited by applicant]
JP 2021536600A · 2021 [cited by applicant]
TW 202040578A · 2020 [cited by applicant]
TW 202133163A · 2021 [cited by applicant]
WO 20080151661A1 · 2008 [cited by applicant]
WO 2020040893A1 · 2020 [cited by applicant]
Taiwanese Office Action mailed on Feb. 20, 2025 corresponding to Taiwanese Patent Application No. 112103391. (Google English Translations and the Taiwanese Office Action are attached.). [cited by applicant]
Taiwanese Office Action mailed on Feb. 11, 2025 corresponding to Taiwanese Patent Application No. 112103390. (Google English Translations and the Taiwanese Office Action are attached.). [cited by applicant]
Taiwanese Office Action mailed on Mar. 11, 2024 corresponding to the related Taiwanese Patent Application No. 112103390. [cited by applicant]
Taiwanese Office Action mailed on Mar. 11, 2024 corresponding to the related Taiwanese Patent Application No. 112103391. [cited by applicant]
PCT Invitation to Pay Additional Fees mailed on Oct. 27, 2022 corresponding to the related PCT Patent Application No. US2022/026363. [cited by applicant]
PCT Search Report and Written Opinion mailed on Dec. 19, 2022 corresponding to the related PCT Patent Application No. US2022/026363. [cited by applicant]
Taiwanese Office Action mailed on Aug. 5, 2024 corresponding to Taiwanese Patent Application No. 112103390. (Google English Translations and the Taiwanese Office Action are attached.). [cited by applicant]
Machine translation of Office Action from Japanese Patent Office, filed under Japan Application No. 2024-537377, 4 pages. [cited by applicant]