Gate driving circuit and display device
A gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first driving circuit includes 1 st to N th first shift registers that are configured to output 1 st to N th first scan signals to N number of scan lines, respectively. The second driving circuit includes 1 st to N th second shift registers that are configured to output 1 st to N th second scan signals to the other N number of scan lines, respectively. The number of transistors in each of the 1 st to N th second shift registers is less than the number of transistors in each of the 1 st to N th first shift registers.
1 . A display device, comprising:
a display panel having an active area and a peripheral area and comprising a plurality of scan lines in the active area, wherein the plurality of scan lines are arranged in a first direction, each of the plurality of scan lines extends in a second direction, the peripheral area comprises a first sub-peripheral area and a second sub-peripheral area that are respectively outside two opposite sides of the active area along the second direction, the plurality of scan lines comprise N number of first scan lines and N number of second scan lines, and the first scan lines and the second scan lines are alternately arranged along the first direction, where N is an integer greater than or equal to 4; and
a gate driving circuit located in the peripheral area and configured to drive the scan lines of the display panel, the gate driving circuit comprising:
a first gate driving circuit located in the first sub-peripheral area and comprising 1 st to N th stage first shift registers that are configured to respectively output 1 st to N th stage first scan signals to the first scan lines; and
a second gate driving circuit located in the second sub-peripheral area and comprising 1 st to N th stage second shift registers that are configured to respectively output 1 st to N th stage second scan signals to second scan lines;
wherein each of the 1 st to N th stage first shift registers and the 1 st to N th stage second shift registers includes a precharge unit and a pull-up unit, the first scan lines are coupled with the pull-up units of the 1 st to N th stage first shift registers and the precharge units of the 1 st to N th stage second shift registers, the second scan lines are coupled with the pull-up units of the 1 st to N th stage second shift registers and not coupled with the 1 st to N th stage first shift registers, and the 1 st to N th stage first scan signals output by the pull-up units of the 1 st to N th stage first shift registers are further transmitted to the precharge units of the 1 st to N th stage second shift registers as a plurality of first input signals of the 1 st to N th stage second shift registers through the first scan lines,
wherein the number of transistors in each of the 1 st to N th stage second shift registers is less than the number of transistors in each of the 1 st to N th stage first shift registers.
2 . The display device of claim 1 , wherein each of the 1 st to N th stage first shift registers has a first width in the second direction, each of the 1 st to N th stage second shift registers has a second width in the second direction, and the first width is greater than the second width.
3 . The display device of claim 2 , wherein the first sub-peripheral area has a first border width in the second direction, the second sub-peripheral area has a second border width in the second direction, and the first border width is greater than the second border width.
4 . The display device of claim 1 , wherein each of the 1 st to N th stage second shift registers is configured to receive a corresponding one of the first input signals, and the first input signal of an i th stage second shift register of the 1 st to N th stage second shift registers is a corresponding one of the 1 st to N th stage first scan signals, where i is an integer greater than or equal to 1 and less than or equal to N.
5 . The display device of claim 4 , wherein each of the 1 st to N th stage second shift registers is configured to further receive a second input signal, the second input signal of a j th stage second shift register of the 1 st to (N−1) th stage second shift registers is a corresponding one of the 1 st to N th stage first scan signals, where j is an integer greater than or equal to 1 and less than or equal to (N−1).
6 . The display device of claim 5 , wherein the first gate driving circuit further comprises a dummy shift register that is configured to receive one of the 1 st to N th stage first scan signals and output a dummy scan signal, and wherein the second input signal of the N th stage second shift register is the dummy scan signal.
7 . The display device of claim 5 , wherein the second gate driving circuit further comprises a scan control signal line that is coupled to the N th stage second shift register, and wherein the second input signal of the N th stage second shift register is a scan control signal that is provided by the scan control signal line.
8 . The display device of claim 1 , wherein the second gate driving circuit further comprises at least one clock signal line, and wherein an i th stage second shift register of the 1 st to N- th stage second shift registers comprises:
a first transistor, wherein a first terminal of the first transistor is configured to receive a first voltage signal, a second terminal of the first transistor is coupled to a first node, and a control terminal of the first transistor is configured to receive a first input signal;
a second transistor, wherein a first terminal of the second transistor is configured to receive a second voltage signal, a second terminal of the second transistor is coupled to the first node, and a control terminal of the second transistor is configured to receive a second input signal; and
a third transistor, wherein a first terminal of the third transistor is configured to receive a clock signal that is provided by one of the at least one clock signal line, a second terminal of the third transistor is coupled to a second node and is configured to output an i th stage second scan signal of the 1 st to N th stage second scan signals, and a control terminal of the second transistor is coupled to the first node, where i is an integer greater than or equal to 1 and less than or equal to N.
9 . The display device of claim 8 , wherein the i th stage second shift register further comprises:
a fourth transistor, wherein a first terminal of the fourth transistor is configured to receive a first reference voltage, and a control terminal of the fourth transistor is coupled to the first node;
a fifth transistor, wherein a first terminal of the fifth transistor is configured to receive the first reference voltage, a second terminal of the fifth transistor is coupled to the first node, and a control terminal of the fifth transistor is coupled to a second terminal of the fourth transistor;
a sixth transistor, wherein a first terminal of the sixth transistor is configured to receive the first reference voltage, a second terminal of the sixth transistor is coupled to the second node, and a control terminal of the sixth transistor is coupled to the second terminal of the fourth transistor; and
a seventh transistor, wherein a first terminal and a control terminal of the seventh transistor is configured to receive a second reference voltage, and a second terminal of the seventh transistor is coupled to the second terminal of the fourth transistor, and the second reference voltage is greater than the first reference voltage.