Electronic device and manufacturing method thereof
An electronic device and a manufacturing method thereof are provided. The electronic device includes an antenna structure, a first circuit structure, and a chip. The antenna structure includes a first dielectric layer, a first metal pattern, a second dielectric layer, and a second metal pattern. The first dielectric layer has a first surface and a second surface. The first metal pattern is disposed on the first surface. The second dielectric layer is disposed on the first metal pattern. The second metal pattern is disposed on the second dielectric layer. The first circuit structure is disposed on the antenna structure, and includes a third dielectric layer, a first conductive layer, and a first pad. The third dielectric layer is disposed on the second surface and has a fourth surface away from the second surface. The first conductive layer is disposed on the fourth surface. The first pad is disposed on the first conductive layer. The chip is disposed on the first circuit structure and electrically connected to the first circuit structure. The first metal pattern is indirectly electrically connected to the first conductive layer. The electronic device and the manufacturing method thereof may increase a bandwidth, reduce warpage, or improve reliability.
1 . An electronic device, comprising:
an antenna structure, comprising:
a first dielectric layer having a first surface and a second surface;
a first metal pattern disposed on the first surface;
a second dielectric layer disposed on the first metal pattern; and
a second metal pattern disposed on the second dielectric layer;
a first circuit structure disposed on the antenna structure and comprising:
a third dielectric layer disposed on the second surface and having a fourth surface away from the second surface;
a first conductive layer disposed on the fourth surface; and
a first pad disposed on the first conductive layer;
a chip disposed on the first circuit structure and electrically connected to the first circuit structure; and
a second circuit structure disposed on the first circuit structure and comprising:
a fourth dielectric layer disposed on the first pad;
a fifth dielectric layer disposed on the fourth dielectric layer;
a second pad disposed on the fifth dielectric layer;
a through hole penetrating through the fourth dielectric layer, the fifth dielectric layer, and the second pad; and
a conductive member disposed on the second pad and in the through hole,
wherein the first metal pattern is indirectly electrically connected to the first conductive layer,
wherein the second pad is electrically connected to the first pad through the conductive member.
2 . The electronic device according to claim 1 , wherein the conductive member is in contact with the second pad.
3 . The electronic device according to claim 1 , wherein the second circuit structure further comprises:
a second conductive layer disposed between the second pad and the fifth dielectric layer,
wherein the through hole penetrates through the second conductive layer.
4 . The electronic device according to claim 3 , wherein the second pad is in contact with the second conductive layer.
5 . The electronic device according to claim 3 , wherein the chip is electrically connected to the first conductive layer through the second conductive layer, the conductive member, and the first pad.
6 . The electronic device according to claim 1 , wherein the first metal pattern overlaps the second metal pattern.
7 . The electronic device according to claim 1 , wherein the second dielectric layer is in direct contact with the first dielectric layer.
8 . The electronic device according to claim 1 , wherein the antenna structure further comprises:
an adhesive material layer disposed between the second dielectric layer and the first dielectric layer.
9 . The electronic device according to claim 1 , wherein the antenna structure further comprises:
a first stress adjustment layer disposed between the first metal pattern and the first dielectric layer,
wherein a coefficient of thermal expansion of the first adjustment adjust layer is between a coefficient of thermal expansion of the first metal pattern and a coefficient of thermal expansion of the first dielectric layer.
10 . The electronic device according to claim 9 , wherein the coefficient of thermal expansion of the first stress adjustment layer is greater than 5 and less than 14.
11 . The electronic device according to claim 9 , wherein a ratio of a thickness of the first stress adjustment layer to a thickness of the first dielectric layer is 0.0001 to 0.01.
12 . The electronic device according to claim 9 , wherein a ratio of a thickness of the first stress adjustment layer to a thickness of the first metal pattern is 0.025 to 4.0.
13 . The electronic device according to claim 9 , wherein the first stress adjustment layer has an opening, and the antenna structure further comprises:
a second stress adjustment layer disposed in the opening,
wherein a coefficient of thermal expansion of the second stress adjustment layer is between the coefficient of thermal expansion of the first metal pattern and the coefficient of thermal expansion of the first dielectric layer.
14 . A manufacturing method of an electronic device, comprising:
forming an antenna structure, wherein the antenna structure comprises:
a first dielectric layer having a first surface and a second surface;
a first metal pattern disposed on the first surface;
a second dielectric layer disposed on the first metal pattern; and
a second metal pattern disposed on the second dielectric layer;
forming a first circuit structure, wherein the first circuit structure comprises:
a third dielectric layer disposed on the second surface and having a fourth surface away from the second surface;
a first conductive layer disposed on the fourth surface; and
a first pad disposed on the first conductive layer; and
bonding the antenna structure and the first circuit structure;
forming a second circuit structure on the first circuit structure, wherein the second circuit structure comprises:
a fourth dielectric layer disposed on the first pad;
a fifth dielectric layer disposed on the fourth dielectric layer;
a second pad disposed on the fifth dielectric layer;
a through hole penetrating through the fourth dielectric layer, the fifth dielectric layer, and the second pad; and
a conductive member disposed on the second pad and in the through hole; and
disposing a chip on the first circuit structure, so that the chip is electrically connected to the first circuit structure,
wherein the first metal pattern is indirectly electrically connected to the first conductive layer,
wherein the second pad is electrically connected to the first pad through the conductive member.
15 . The manufacturing method according to claim 14 , wherein the second circuit structure further comprises:
a second conductive layer disposed between the second pad and the fifth dielectric layer,
wherein the through hole penetrates through the second conductive layer.
16 . The manufacturing method according to claim 14 , wherein the antenna structure further comprises:
an adhesive material layer disposed between the second dielectric layer and the first dielectric layer.
17 . The manufacturing method according to claim 14 , further comprising:
forming a first stress adjustment layer between the first metal pattern and the first dielectric layer,
wherein a coefficient of thermal expansion of the first adjustment adjust layer is between a coefficient of thermal expansion of the first metal pattern and a coefficient of thermal expansion of the first dielectric layer.
18 . The manufacturing method according to claim 17 , wherein the first stress adjustment layer has an opening, and the manufacturing method further comprises:
forming a second stress adjustment layer in the opening,
wherein a coefficient of thermal expansion of the second stress adjustment layer is between the coefficient of thermal expansion of the first metal pattern and the coefficient of thermal expansion of the first dielectric layer.