Voltage regulator with latched cycle-by-cycle current limit indicator
Systems and methods for a cycle-by-cycle current limit event indicator is described. A circuit can include receiving a plurality of signals indicating occurrences of a plurality of overcurrent events over a plurality of clock cycles in a voltage regulator. The circuit can further include generating a latch signal to indicate the occurrences of the plurality of overcurrent events over the plurality of clock cycles. The latch signal can remain latched at high voltage for a number of clock cycles.
1 . A method comprising:
receiving a plurality of signals indicating occurrences of a plurality of overcurrent events over a plurality of clock cycles in a voltage regulator; and
generating a latch signal to indicate the occurrences of the plurality of overcurrent events over the plurality of clock cycles, wherein the latch signal remains latched at high voltage for a number of clock cycles.
2 . The method of claim 1 , wherein the number of clock cycles is based on a programmable delay to delay a falling edge of the latch signal.
3 . The method of claim 1 , wherein the voltage regulator is a single phase voltage regulator.
4 . The method of claim 1 , wherein the voltage regulator is a multi-phase voltage regulator.
5 . The method of claim 1 , further comprising determining, based on the latch signal, a time duration for an output voltage of the voltage regulator to reach a regulated voltage.
6 . The method of claim 1 , further comprising:
receiving, in a first clock cycle among the plurality of clock cycles, a first signal among the plurality of signals, the first signal indicating a presence of a overcurrent event in the voltage regulator;
in response to receiving the first signal indicating the presence of the overcurrent event in the first clock cycle, latching the latch signal at high voltage;
receiving, in a second clock cycle among the plurality of clock cycles, a second signal among the plurality of signals, the second signal indicating an absence of a overcurrent event in a voltage regulator; and
in response to receiving the second signal indicating the absence of the overcurrent event in the second clock cycle, maintaining the latch signal at high voltage.
7 . The method of claim 1 , further comprising:
receiving, in a first clock cycle among the plurality of clock cycles, a first signal among the plurality of signals, the first signal indicating a presence of a overcurrent event in the voltage regulator;
in response to receiving the first signal indicating the presence of the overcurrent event in the first clock cycle, latching the latch signal at high voltage;
receiving, in a second clock cycle among the plurality of clock cycles, a second signal among the plurality of signals, the second signal indicating an absence of a overcurrent event in a voltage regulator;
in response to receiving the second signal indicating the absence of the overcurrent event in the second clock cycle, maintaining the latch signal at high voltage;
receiving, in a third clock cycle among the plurality of clock cycles, a third signal among the plurality of signals, the third signal indicating another presence of a overcurrent event in a voltage regulator; and
in response to receiving the third signal indicating the presence of the overcurrent event in the third clock cycle, maintaining the latch signal at high voltage.
8 . A semiconductor device comprising:
at least one flip-flop;
a latch circuit configured to:
receive a plurality of signals indicating occurrences of a plurality of overcurrent events over a plurality of clock cycles in a voltage regulator; and
generate a latch signal to indicate the occurrences of the plurality of overcurrent events over the plurality of clock cycles, wherein the latch signal remains latched at high voltage for a number of clock cycles, and the number of clock cycles is based on a number of flip-flops among the at least one flip-flop.
9 . The semiconductor device of claim 8 , wherein:
the at least one flip-flop comprises at least one D-type flip-flop; and
the latch circuit is a S-R latch.
10 . The semiconductor device of claim 8 , wherein the voltage regulator is a single phase voltage regulator.
11 . The semiconductor device of claim 8 , wherein the voltage regulator is a multi-phase voltage regulator.
12 . The semiconductor device of claim 8 , wherein a time duration for an output voltage of the voltage regulator to reach a regulated voltage is indicated by the latch signal.
13 . The semiconductor device of claim 8 , wherein the latch circuit is further configured to:
receive, in a first clock cycle among the plurality of clock cycles, a first signal among the plurality of signals, the first signal indicating a presence of a overcurrent event in the voltage regulator;
in response to receipt of the first signal indicating the presence of the overcurrent event in the first clock cycle, latch the latch signal at high voltage;
receive, in a second clock cycle among the plurality of clock cycles, a second signal among the plurality of signals, the second signal indicating an absence of a overcurrent event in a voltage regulator; and
in response to receipt of the second signal indicating the absence of the overcurrent event in the second clock cycle, maintain the latch signal at high voltage.
14 . The semiconductor device of claim 8 , wherein the latch circuit is further configured to:
receive, in a first clock cycle among the plurality of clock cycles, a first signal among the plurality of signals, the first signal indicating a presence of a overcurrent event in the voltage regulator;
in response to receipt of the first signal indicating the presence of the overcurrent event in the first clock cycle, latch the latch signal at high voltage;
receive, in a second clock cycle among the plurality of clock cycles, a second signal among the plurality of signals, the second signal indicating an absence of a overcurrent event in a voltage regulator; and
in response to receipt of the second signal indicating the absence of the overcurrent event in the second clock cycle, maintain the latch signal at high voltage;
receive, in a third clock cycle among the plurality of clock cycles, a third signal among the plurality of signals, the third signal indicating another presence of a overcurrent event in a voltage regulator; and
in response to receipt of the third signal indicating the presence of the overcurrent event in the third clock cycle, maintain the latch signal at high voltage.
15 . A system comprising:
a controller configured to detect occurrences of overcurrent events in a voltage regulator;
a circuit configured to:
receive a plurality of signals from the controller indicating occurrences of a plurality of overcurrent events over a plurality of clock cycles in the voltage regulator; and
generate a latch signal to indicate the occurrences of the plurality of overcurrent events over the plurality of clock cycles, wherein the latch signal remains latched at high voltage for a number of clock cycles.
16 . The system of claim 15 , wherein the number of clock cycles is based on a programmable delay to delay a falling edge of the latch signal.
17 . The system of claim 15 , wherein the voltage regulator is a single phase voltage regulator.
18 . The system of claim 15 , wherein the voltage regulator is a multi-phase voltage regulator.
19 . The system of claim 15 , wherein the circuit is further configured to:
receive, in a first clock cycle among the plurality of clock cycles, a first signal among the plurality of signals, the first signal indicating a presence of a overcurrent event in the voltage regulator;
in response to receipt of the first signal indicating the presence of the overcurrent event in the first clock cycle, latch the latch signal at high voltage;
receive, in a second clock cycle among the plurality of clock cycles, a second signal among the plurality of signals, the second signal indicating an absence of a overcurrent event in a voltage regulator; and
in response to receipt of the second signal indicating the absence of the overcurrent event in the second clock cycle, maintain the latch signal at high voltage.
20 . The system of claim 15 , wherein the circuit is further configured to:
receive, in a first clock cycle among the plurality of clock cycles, a first signal among the plurality of signals, the first signal indicating a presence of a overcurrent event in the voltage regulator;
in response to receipt of the first signal indicating the presence of the overcurrent event in the first clock cycle, latch the latch signal at high voltage;
receive, in a second clock cycle among the plurality of clock cycles, a second signal among the plurality of signals, the second signal indicating an absence of a overcurrent event in a voltage regulator; and
in response to receipt of the second signal indicating the absence of the overcurrent event in the second clock cycle, maintain the latch signal at high voltage;
receive, in a third clock cycle among the plurality of clock cycles, a third signal among the plurality of signals, the third signal indicating another presence of a overcurrent event in a voltage regulator; and
in response to receipt of the third signal indicating the presence of the overcurrent event in the third clock cycle, maintain the latch signal at high voltage.