IP Library Granted Patent US 12,640,702
Granted Patent B2
US 12,640,702 · App. 17/067,518 · Granted May 26, 2026

Josephson wide band multiplexer-demultiplexer circuit

Inventors: Matthew Beck (Danbury, CT); Joseph Allen Glick (Putnam Valley, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H03H7/46G06N10/40H03H7/0123H03H7/09H03H7/1775H03H7/465H10N60/12H10N60/805
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,640,702
App. No.
17/067,518
Granted
May 26, 2026
Kind
B2
Abstract

A superconducting circuit includes a first port and a plurality of second ports; a plurality of filter poles, each filter pole comprising an inductor and a capacitor connected in parallel, between the first port and a second port in the plurality of second ports; an admittance inverter comprising at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter linking two successive filter poles together. The plurality of filter poles and associated admittance inverters define a plurality of current branches so that, when operating as a demultiplexer, an input electrical current input though the first port is routed to a selected one of the plurality of the plurality of second ports by an application of a first set of magnetic flux biases.

Claims (24)

1 . A superconducting circuit comprising:

a first port and a plurality of second ports;

a plurality of filter poles, each filter pole comprising an inductor and a capacitor connected in parallel, between the first port and a second port in the plurality of second ports, wherein the plurality of filter poles comprises greater than 2 filter poles;

an admittance inverter comprising at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter linking two successive filter poles together,

wherein at least one filter pole of the plurality of filter poles together with the admittance inverter define a current branch (IB), and

wherein a first configuration of the plurality of filter poles and a second configuration of the associated admittance inverters define a plurality of current branches so that:

the superconducting circuit is adapted such that an input electrical current input through the first port is routed to a selected one of the plurality of the plurality of second ports by an application of a first set of magnetic flux biases, wherein the single magnetic flux bias feeds and is connected to each of multiple ones of the plurality of filter poles for a defined stage; and

the superconducting circuit is adapted such that an input electrical current input through any one of the plurality of second ports is routed as an output electrical current output through the first port by the application of a second set of magnetic flux biases, wherein the single magnetic flux bias feeds and is connected to each of multiple ones of the plurality of filter poles for the defined stage.

2 . The circuit according to claim 1 , wherein the first set magnetic flux biases is applied to match a current output through the selected one of the plurality of second ports to the current input through the first port, and all remaining not-selected ones of the plurality of second ports are mismatched from the first port and have essentially zero transmission.

3 . The circuit according to claim 1 , wherein the inductor and the capacitor in each filter pole are connected to electrical ground and to the Josephson junction and to the coupling capacitor of adjacent ones of the admittance inverters, and wherein the plurality of filter poles comprises 8 filter poles.

4 . The circuit according to claim 3 , wherein the coupling capacitor is configured to decouple, from direct current (DC), two filter poles of the plurality of filter poles.

5 . The circuit according to claim 1 , wherein the current branch comprises one filter pole or two filter poles of the plurality of filter poles, wherein the current branch is one of the plurality of current branches.

6 . The circuit according to claim 1 , wherein a number of second ports is dependent on a number of current branches.

7 . The circuit according to claim 6 , wherein the plurality of second ports is equal to N/2, where N−1 is a number of total current branches, wherein N is an even integer.

8 . The circuit according to claim 1 , wherein a number of the plurality of second ports is equal to 2 P/2, where P is a number of filter poles of the plurality of filter poles in an arm from the first port to a second port in the plurality of second ports, for an even number P of the plurality of filter poles.

9 . The circuit according to claim 1 , wherein the first port is connected to a first current branch having a first filter pole and each of the plurality of second ports is connected to a corresponding second current branch having a corresponding second pole.

10 . The circuit according to claim 1 , wherein the first port is connected to a first current branch via a first capacitor and each of the plurality of second ports is connected to a second current branch via a corresponding second capacitor, wherein the first current branch and the second current branch are ones of the plurality of current branches, and wherein the circuit comprises at least two intermediary branches of the plurality of current branches and the at least two intermediate branches are coupled to at least four of the plurality of current branches, wherein the at least four of the plurality of current branches are coupled to at least eight of the plurality of current branches.

11 . The circuit according to claim 1 , wherein each of the plurality of current branches in an arm from the first port to a second port in the plurality of second ports is structurally adapted to operate in a selected frequency range based on selected operating parameters.

12 . The circuit according to claim 11 , wherein the selected frequency range is from 4 GHz to 8 GHz.

13 . The circuit according to claim 1 , wherein based on a current being input through the first port, the current is selectively transmitted to a second port in the plurality of second ports by applying external flux biases.

14 . The circuit according to claim 1 , wherein an impedance of the plurality of filter poles is selected such that a beta-L coefficient (fk) of each superconducting quantum interference device (SQUID) loop including the Josephson junction and an inductor of a filter pole of the plurality of filter poles is less than one,

wherein fk=21t*lc*L/<1>0, where Lis the geometric inductance of the SQUID, Ic is the critical current of the coupling JJ, and <1>o is a superconducting magnetic flux quantum.

15 . The circuit according to claim 1 , wherein an impedance at the first port is matched with an impedance of each of the plurality of second ports.

16 . The circuit according to claim 1 , wherein an impedance at the first port is not matched with an impedance of each of the plurality of second ports.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2022
From: BECK, MATTHEW; GLICK, JOSEPH ALLEN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 060502/0892 →
Continuity (1)
Related Publication 20220115577A1 · Apr 14, 2022
References Cited (30)
US 3764905A · Zappe · 1973 [cited by applicant]
US 4533840A · Gheewala et al. · 1985 [cited by applicant]
US 9768771B2 · Naaman · 2017 [cited by applicant]
US 9917580B2 · Naaman · 2018 [cited by applicant]
US 10164606B1 · Keane · 2018 [cited by examiner]
US 10505097B1 · Inamdar et al. · 2019 [cited by applicant]
US 20170033815A1 · Leipold · 2017 [cited by examiner]
US 20190385088A1 · Naaman et al. · 2019 [cited by applicant]
CN 1184930A · 1998 [cited by applicant]
CN 1067768C · 2001 [cited by applicant]
CN 101059556A · 2007 [cited by applicant]
CN 109062597A · 2018 [cited by applicant]
JP 2011524131A · 2011 [cited by applicant]
JP 2019530336A · 2019 [cited by applicant]
WO 2019236137A2 · 2019 [cited by applicant]
O. Naaman; M. O. Abutaleb; C. Kirby; M. Rennie; On-chip Josephson junction microwave switch; Appl. Phys. Lett. 108, 112601 (2016) (Year: 2016). [cited by examiner]
Examination Report No. 1 received for Australian Patent Application Serial No. 2021356089 dated Aug. 31, 2023, 3 pages. [cited by applicant]
Response to the Communication pursuant to Rules 161(1) and 162 EPC received for European Patent Application Serial No. EP21786961.9 dated Nov. 27, 2023, 4 pages. [cited by applicant]
Naaman O et al., “On-chip Josephson junction microwave switch”, Applied Physics Letters, American Institute of Physics, vol. 108, No. 11, Mar. 14, 2016, pp. 112601-1-112601-4, XPO12205944. [cited by applicant]
Naaman O et al., “On-chip Josephson junction microwave switch”, arXiv: 1512.01484v1[cond-mat.sur-con] Dec. 4, 2015. [cited by applicant]
PCT/EP2021/077524 International Search Report mailed Mar. 28, 2022. [cited by applicant]
PCT/EP2021/077524 Written Opinion mailed Mar. 28, 2022. [cited by applicant]
Invitation to Pay Additional Fees received for International PCT Application Serial No. PCT/EP2021/077524 dated Feb. 7, 2022, 14 pages. [cited by applicant]
Pechal et al., “Superconducting Switch for Fast On-Chip Routing of Quantum Microwave Fields”, Physical Review Applied, vol. 6, 2016, pp. 024009-1-024009-8. [cited by applicant]
Sliwa et al., “Reconfigurable Josephson Circulator/Directional Amplifier”, Physical Review X, vol. 5, 2015, pp. 041020-1-041020-10. [cited by applicant]
Hornibrook et al., “Cryogenic Control Architecture for Large-Scale Quantum Computing”, Physical Review Applied, vol. 3, 2015, pp. 024010-1-024010-9. [cited by applicant]
Attar et al., “Low Temperature Superconducting RF MEMS Devices”, IEEE Transactions on Applied Superconductivity, vol. 23, No. 3, Jun. 2013, 4 pages. [cited by applicant]
Namaan et al., Appl. Phys. Lett. 108, 112601 (2016). [cited by applicant]
Abdo, B. et al., Nature Comm. 10, 3154 (2019). [cited by applicant]
Japanese Patent Office “Notice of Reasons for Refusal” Feb. 25, 2025, Japanese Patent Application No. 2023-515332, 7 pages. [cited by applicant]