Granted Patent B2

US 12,640,907 · App. 18/187,630 · Granted May 26, 2026

Inventor: Matthew Brandon Robinson (Millersville, MD)

Assignee: Rampart Communications, Inc.

H04L9/0637H04L27/2627H04L2209/80

Abstract

Claims (40)

1 . A non-transitory, processor-readable medium storing instructions that, when executed by a processor, cause the processor to:

receive a first vector comprising a plurality of symbols;

partition the first vector to produce a magnitude vector comprising magnitude values of each symbol in the plurality of symbols and a sign vector comprising sign values of each symbol in the plurality of symbols;

generate a second vector that includes a modified magnitude vector and a modified sign vector, by:

applying a permutation to the magnitude vector to produce the modified magnitude vector,

converting the sign vector, based on an algorithm, into an intermediate sign vector, and

applying a sequenced plurality of sets of nonlinear transformations to the intermediate sign vector, to produce the modified sign vector, wherein an encryption mode of operation of the processor is one of a cipher block chaining (CBC) mode or an electronic code book (ECB) mode;

apply a sequenced plurality of sets of linear transformations to the second vector to produce a third vector, the third vector being a transformed version of the first vector, wherein at least one of a number of sets of linear transformations from the plurality of sets of linear transformations or a number of sets of nonlinear transformations from the plurality of sets of nonlinear transformations is equal to log 2 (N), wherein Nis an integer; and

cause transmission of a first signal representing the third vector to at least one transmitter for transmission of a second signal representing the transformed version of the first vector from the at least one transmitter to at least one receiver.

2 . The non-transitory, processor-readable medium of claim 1 , wherein the instructions further comprise instructions to cause the processor to select the algorithm based on the encryption mode of operation of the processor, and the instructions to convert the sign vector include instructions to convert the sign vector based on an initialization vector.

3 . The non-transitory, processor-readable medium of claim 1 , wherein the instructions further comprise instructions to cause the processor to select the algorithm based on the encryption mode of operation of the processor, and the encryption mode of operation of the processor is one of a cipher block chaining (CBC) mode or an electronic code book (ECB) mode.

4 . The non-transitory, processor-readable medium of claim 1 , wherein the algorithm includes an Xor operation, the encryption mode of operation of the processor is a cipher block chaining (CBC) mode, and the permutation applied to the magnitude vector does not reduce a total power of the first vector.

5 . The non-transitory, processor-readable medium of claim 1 , wherein the algorithm includes an Xor operation, the encryption mode of operation of the processor is an electronic code book (ECB) mode, and the permutation applied to the magnitude vector does not reduce a total power of the first vector.

6 . The non-transitory, processor-readable medium of claim 1 , wherein:

the number of sets of nonlinear transformations from the plurality of sets of nonlinear transformations equals the number of sets of linear transformations from the plurality of sets of linear transformations; and

the algorithm is selected based on the encryption mode of operation of the processor.

7 . The non-transitory, processor-readable medium of claim 1 , wherein:

the number of sets of nonlinear transformations from the plurality of sets of nonlinear transformations is different from the number of sets of linear transformations in the plurality of sets of linear transformations; and

the algorithm is selected based on the encryption mode of operation of the processor.

8 . The non-transitory, processor-readable medium of claim 1 , wherein:

at least one of the number of sets of nonlinear transformations from the plurality of sets of nonlinear transformations or the number of sets of linear transformations from the plurality of sets of linear transformations is based on a performance constraint.

9 . The non-transitory, processor-readable medium of claim 1 , wherein:

at least one of the number of sets of nonlinear transformations from the plurality of sets of nonlinear transformations or the number of sets of linear transformations from the plurality of sets of linear transformations is based on a security constraint.

10 . The non-transitory, processor-readable medium of claim 1 , wherein:

the algorithm is selected based on an encryption mode of operation of the processor; and

the permutation applied to the magnitude vector does not reduce a total power of the first vector.

11 . A system, comprising a processor and a memory operably coupled to the processor, the memory storing instructions that, when executed by the processor, cause the processor to:

receive an input vector comprising a plurality of symbols;

generate a transformed vector based on the input vector, by:

applying a permutation to a magnitude vector comprising magnitude values of each symbol in the plurality of symbols of the input vector, to produce a modified magnitude vector,

applying an algorithm and a sequenced plurality of sets of nonlinear transformations to a sign vector comprising sign values of each symbol in the plurality of symbols of the input vector, to produce a modified sign vector, the modified magnitude vector and the modified sign vector defining an intermediate vector, wherein an encryption mode of operation of the processor is one of a cipher block chaining (CBC) mode or an electronic code book (ECB) mode, and

applying a sequenced plurality of sets of linear transformations to the intermediate vector to produce the transformed vector, wherein at least one of a number of sets of linear transformations from the plurality of sets of linear transformations or a number of sets of nonlinear transformations from the plurality of sets of linear transformations is equal to [log 2 (N)], where Nis an integer; and

cause transmission of a signal representing the transformed vector to at least one transmitter.

12 . The system of claim 11 , wherein the plurality of sets of nonlinear transformations includes at least two of: a permutation, an S-box transformation, a diffusive linear operation, or an Xor operation.

13 . The system of claim 12 , wherein the memory further stores instructions to cause the processor to select the algorithm based on the encryption mode of operation of the processor.

14 . The system of claim 11 , wherein the algorithm includes an Xor operation, and the algorithm is selected based on an encryption mode of operation of the processor.

15 . The system of claim 11 , wherein the number of sets of nonlinear transformations from the plurality of sets of nonlinear transformations equals the number of sets of linear transformations in the plurality of sets of linear transformations.

16 . The system of claim 11 , wherein the number of sets of nonlinear transformations from the plurality of sets of nonlinear transformations is different from the number of sets of linear transformations from the plurality of sets of linear transformations.

17 . The system of claim 11 , wherein at least one of the number of sets of nonlinear transformations from the plurality of sets of nonlinear transformations or the number of sets of linear transformations from the plurality of sets of linear transformations is based on at least one of a performance constraint or a security constraint.

18 . The system of claim 11 , wherein the permutation applied to the magnitude vector does not reduce a total power of the input vector, and the algorithm is selected based on the encryption mode of operation of the processor.

Assignments (1)

Continuity (2)

References Cited (337)