Multi-port SRAM structure with gate-all-around transistors
A memory cell includes a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, and a third active region providing a plurality of third nano-structures for a read-port pull-down transistor. The first active region has a first width, the second active region has a second width, and the third active region having a third width. The third width is larger than the first width, and the first width is larger than the second width.
1 . A memory cell, comprising:
a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, the first active region having a first width;
a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, the second active region having a second width; and
a third active region providing a plurality of third nano-structures for a read-port pull-down transistor, the third active region having a third width,
wherein the third width is larger than the first width, and the first width is larger than the second width.
2 . The memory cell of claim 1 , wherein a ratio of the first width and the second width ranges from about 1.5:1 to about 5:1.
3 . The memory cell of claim 1 , wherein a ratio of the third width and the first width ranges from about 1.1:1 to about 3:1.
4 . The memory cell of claim 1 , further comprising:
a gate structure line extending across over the first, second, and third active regions; and
a gate-cut dielectric feature dividing the gate structure line into a first gate structure wrapping each of the first nano-structures and a second gate structure wrapping each of the second and third nano-structures.
5 . The memory cell of claim 4 , wherein the gate-cut dielectric feature extends vertically deeper in a region in the gate structure line than in a region outside of the gate structure line.
6 . The memory cell of claim 4 , wherein the gate-cut dielectric feature is a first gate-cut dielectric feature, the memory cell further comprising:
a second gate-cut dielectric feature abutting the second gate structure.
7 . The memory cell of claim 6 , further comprising:
a backside contact straddling the second gate-cut dielectric feature.
8 . The memory cell of claim 1 , further comprising:
a fourth active region providing a plurality of fourth nano-structures for a write-port pull-down transistor, the fourth active region having a fourth width,
wherein the third width is larger than the fourth width, and the fourth width is larger than the second width.
9 . The memory cell of claim 8 , wherein the fourth width is different from the first width.
10 . The memory cell of claim 1 , further comprising:
a fourth active region providing a plurality of fourth nano-structures for a write-port pull-up transistor, the fourth active region having a fourth width,
wherein the fourth width is smaller than the first width, and the fourth width is different from the second width.
11 . A semiconductor structure, comprising:
first and second active regions extending lengthwise along a first direction;
a gate stack extending lengthwise along a second direction perpendicular to the first direction;
a dielectric feature disposed between the first and second active regions, wherein the dielectric feature divides the gate stack into a first segment over the first active region and a second segment over the second active region;
a first epitaxial feature disposed on the first active region;
a second epitaxial feature disposed on the second active region, wherein the first and second epitaxial features are disposed on two opposing sides of the dielectric feature; and
a backside conductive feature electrically coupled to the first and second epitaxial features and straddling the dielectric feature.
12 . The semiconductor structure of claim 11 , wherein the dielectric feature extends lengthwise along the first direction.
13 . The semiconductor structure of claim 11 , wherein the backside conductive feature includes a first leg portion landing on a bottom surface of the first epitaxial feature, a second leg portion landing on a bottom surface of the second epitaxial feature, and a middle portion physically connecting the first and second leg portions, wherein the middle portion is directly under the dielectric feature.
14 . The semiconductor structure of claim 13 , wherein the middle portion is in physical contact with the dielectric feature.
15 . The semiconductor structure of claim 11 , further comprising:
a frontside contact disposed on the first and second epitaxial features, wherein the dielectric feature is vertically stacked between the frontside contact and the backside conductive feature.
16 . The semiconductor structure of claim 15 , wherein the frontside contact expands in the second direction wider than the backside conductive feature.
17 . The semiconductor structure of claim 11 , wherein the first and second segments of the gate stack are configured to engage the first and second active regions to form first and second transistors, respectively, in first and second read-ports of first and second memory cells in a memory array.
18 . A semiconductor structure, comprising:
a first memory cell, the first memory cell comprising:
a first active region providing a plurality of first nano-structures for a write-port pull-down transistor of the first memory cell;
a second active region providing a plurality of second nano-structures for a write-port pull-up transistor of the first memory cell; and
a third active region providing a plurality of third nano-structures for a read-port pull-down transistor of the first memory cell;
a second memory cell abutting the first memory cell, the second memory cell comprising:
a fourth active region providing a plurality of fourth nano-structures for a write-port pull-down transistor of the second memory cell;
a fifth active region providing a plurality of fifth nano-structures for a write-port pull-up transistor of the second memory cell; and
a sixth active region providing a plurality of sixth nano-structures for a read-port pull-down transistor of the second memory cell;
a gate structure line extending across over the first, second, third, fourth, fifth, and sixth active regions;
a gate-cut dielectric feature dividing the gate structure line into a first gate structure wrapping each of the first, second, and third nano-structures and a second gate structure wrapping each of the fourth, fifth, and sixth nano-structures; and
a backside contact straddling the gate-cut dielectric feature and in electrical coupling with bottom surfaces of the third and sixth active regions.
19 . The semiconductor structure of claim 18 , wherein the backside contact has a first leg portion in electrical coupling with the bottom surface of the third active region, a second leg portion in electrical coupling with the bottom surface of the sixth active region, and a bridging portion connecting the first and second leg portions.
20 . The semiconductor structure of claim 19 , wherein the bridging portion interfaces with a bottom surface of the gate-cut dielectric feature.