Granted Patent B2

US 12,641,808 · App. 17/958,787 · Granted May 26, 2026

Inventor: Tomohiro Imai (Tokyo, JP)

Assignee: Renesas Electronics Corporation

H10D12/421H10D12/481H10D62/60H10W20/069

Abstract

Claims (41)

1 . A method of manufacturing a semiconductor device comprising the steps of:

(a) preparing a semiconductor substrate having a semiconductor layer of a first conductivity type;

(b) forming a trench in the semiconductor layer;

(c) forming a gate insulating film inside the trench;

(d) forming a gate electrode on the gate insulating film so as to fill an inside of the trench;

(e) forming a first insulating film on the semiconductor layer;

(f) forming a first impurity region of a second conductivity type opposite to the first conductivity type in the semiconductor layer;

(g) forming a second impurity region of the first conductivity type in the first impurity region;

(h) forming a second insulating film having a thickness larger than a thickness of the first insulating film on the first insulating film, thereby forming an interlayer insulating film including the second insulating film and the first insulating film on the semiconductor layer;

(i) forming a contact hole penetrating the interlayer insulating film and the second impurity region and reaching the first impurity region; and

(j) forming a plug electrically connected to the first impurity region and the second impurity region so as to fill an inside of the contact hole,

wherein the first insulating film is a silicon oxide film,

wherein the second insulating film is a BPSG film,

wherein the step of (i) includes:

(i1) forming a first contact hole in the second insulating film, the first insulating film, the second impurity region, and the first impurity region; and

(i2) after the step of (i1), performing isotropic etching process to the second insulating film and the first insulating film, thereby forming, in the second insulating film and the first insulating film, a second contact hole having an opening width larger than an opening width of the first contact hole and communicating with the first contact hole,

wherein in the step of (c), the gate insulating film is formed also on the semiconductor layer outside the trench,

wherein in the step of (e), the first insulating film is formed by performing isotropic etching process to the gate insulating film formed on the semiconductor layer outside the trench, and

wherein the thickness of the first insulating film formed on the semiconductor layer outside the trench is smaller than a thickness of the gate insulating film formed inside the trench.

2 . The method according to claim 1 ,

wherein the thickness of the first insulating film is equal to or smaller than half the thickness of the gate insulating film.

3 . The method according to claim 1 ,

wherein the gate insulating film is formed by thermal oxidation method.

4 . The method according to claim 1 ,

wherein, in the step of (h), the second insulating film is formed by CVD method and then heat treatment is performed to the second insulating film, and

wherein an upper surface of the second insulating film after the heat treatment is more planarized than the upper surface of the second insulating film before the heat treatment.

5 . The method according to claim 4 ,

wherein, in the step of (d), in a semiconductor element formation region of the semiconductor substrate, which is different from a region where the trench is formed, a first conductive film in the same layer as the gate electrode is formed on the semiconductor layer,

wherein in the step of (h), the second insulating film is formed so as to cover the first conductive film in the semiconductor element formation region, and

wherein the thickness of the second insulating film formed on the first conductive film is larger than a thickness of the first conductive film before the heat treatment.

6 . The method according to claim 1 ,

wherein the step of (h) further includes forming a third insulating film having a thickness smaller than the thickness of the second insulating film and made of a PSG film on the first insulating film before forming the second insulating film,

wherein the second insulating film is formed on the third insulating film,

wherein the interlayer insulating film includes the first insulating film, the second insulating film, and the third insulating film,

wherein in the step of (i1), the first contact hole is formed also in the third insulating film, and

wherein in the step of (i2), the isotropic etching process is performed also to the third insulating film and the second contact hole is formed also in the third insulating film.

7 . The method according to claim 1 ,

wherein the step of (j) includes the steps of:

(j1) forming a barrier metal film inside the contact hole;

(j2) performing heat treatment to the barrier metal film, thereby forming a silicide film, which is an alloy film of a metal material contained in the barrier metal film and silicon, on an upper surface and a side surface of the first impurity region inside the contact hole; and

(j3) forming a second conductive film on the barrier metal film so as to fill the inside of the contact hole.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (22)