Regulated mobile ion synapses
A method of making a mobile ion regulated device includes stacking a dielectric layer on a substrate. Mobile ions are placed within the dielectric layer. An electrode layer is provided on the dielectric layer. The mobile ions are directed to a designated area of the dielectric layer.
1 . A mobile ion regulated device, comprising:
a 3-terminal FET device structure including a gate stack comprising a plurality of layers of material filled with mobile ions;
a source, a drain and a gate arranged on a substrate; and
a pulse generator arranged between at least one of the gate and the source, or between the source and the drain,
wherein an arrangement of the plurality of layers of material confines the mobile ions within adjacent ones of the plurality of layers during a voltage bias applied by the pulse generator.
2 . The device according to claim 1 , wherein
the gate comprises a top gate arranged above the substrate.
3 . The device according to claim 1 , wherein:
the gate comprises an embedded gate arranged within a dielectric layer on the substrate;
the gate stack comprises a high-k superlattice; and
wherein the voltage bias controls an arrangement of the mobile ions within the layers of the high-k superlattice.
4 . The device according to claim 3 , wherein the high-K superlattice comprises alternating dielectric material layers having different band gaps.
5 . The device according to claim 1 , wherein:
the 3-terminal FET device structure is configured as an analog synapse; and
wherein the voltage bias is configured to provide a rest state, a depression state, a potentiation state, and a read state based on a respective arrangement of at least the mobile ions within the 3-terminal FET device structure.
6 . The device according to claim 1 , wherein the gate stack comprises layers of a high-k superlattice, and
the voltage bias controls an arrangement of the mobile ions within the layers of the high-k superlattice.
7 . The device according to claim 6 , wherein the layers of the high-k superlattice comprise alternating dielectric material layers having different band gaps.
8 . The device according to claim 7 , wherein each layer of the alternating dielectric material layers confines some of the mobile ions.
9 . The device according to claim 7 , wherein the voltage bias controls an arrangement of the mobile ions within each layer of the alternating dielectric material layers.
10 . A 3-terminal FET device, comprising:
a substrate;
a source arranged on the substrate;
a drain arranged on the substrate;
a gate stack arranged on the substrate between the source and the drain and comprising a plurality of layers of a high-k superlattice comprising alternating dielectric material layers having different band gaps, wherein each of layer of the plurality of layers includes mobile ions; and
a top gate arranged on the gate stack.
11 . The 3-terminal FET device of claim 10 , configured as an analog synapse including a pulse generator arranged between at least one of the top gate and the source or between the source and the drain,
wherein a voltage bias applied by the pulse generator is configured to provide a rest state, a depression state, a potentiation state, and a read state negative based on a respective arrangement of the mobile ions within the alternating dielectric material layers.
12 . The 3-terminal FET device of claim 10 , wherein a voltage bias controls an arrangement of the mobile ions within the plurality of layers of the high-k superlattice.
13 . The 3-terminal FET device of claim 12 , wherein each layer of the alternating dielectric material layers confines some of the mobile ions.
14 . The 3-terminal FET device of claim 13 , wherein the voltage bias is configured to control arrangement of the mobile ions within each layer of the alternating dielectric material layers.