Non-silicon semiconductor complementary thin film transistor, method of manufacturing the same, and pixel structure including the complementary thin film transistor
A complementary thin film transistor (TFT) includes a substrate and a first TFT and a second TFT disposed on the substrate, wherein a first conductive semiconductor layer of the first TFT and a second gate electrode layer of the second TFT are disposed in the same layer and include the same material.
1 . A complementary thin film transistor (TFT) comprising:
a substrate; and
a first TFT and a second TFT disposed on the substrate,
wherein a first conductive semiconductor layer of the first TFT and a second gate electrode layer of the second TFT are disposed in a same layer and include a same material.
2 . The complementary TFT of claim 1 , wherein the first TFT comprises:
a gate insulation layer disposed on the first conductive semiconductor layer;
a first source electrode layer and a first drain electrode layer disposed on the gate insulation layer and electrically connected with the first conductive semiconductor layer through a first contact hole patterned in the gate insulation layer; and
a first gate electrode layer disposed between the first source electrode layer and the first drain electrode layer.
3 . The complementary TFT of claim 1 , wherein the substrate is a non-silicon substrate having a low heat resistance temperature, and
the non-silicon substrate is a glass substrate.
4 . The complementary TFT of claim 1 , wherein the substrate, the first TFT, and the second TFT are included in a complementary metal oxide semiconductor (CMOS) logic circuit including a CMOS inverter, a CMOS NAND circuit, a CMOS NOR circuit, a CMOS AND circuit, and a CMOS OR circuit, a CMOS arithmetic logic unit (ALU), a CMOS microprocessor, a CMOS RFID TAG circuit, a CMOS image sensor, and a display pixel circuit.
5 . The complementary TFT of claim 1 , wherein the first conductive semiconductor layer is an n-type semiconductor layer or a p-type semiconductor layer,
when the first conductive semiconductor layer is the n-type semiconductor layer, the second gate electrode layer comprises the same material as a material of the n-type semiconductor layer, and
when the first conductive semiconductor layer is the p-type semiconductor layer, the second gate electrode layer comprises the same material as a material of the p-type semiconductor layer.
6 . The complementary TFT of claim 5 , wherein the n-type semiconductor layer comprises one material of a zinc oxide (ZnO)-based material, an indium oxide (InO)-based material, a tin oxide (SnO)-based material, a titanium oxide (TiO)-based material, an indium-gallium-zinc oxide (InGaZnO)-based material, a manganese-tin-indium oxide (ZnSnInO)-based material, an indium tin oxide (InSnO)-based material, and a combination of at least two materials thereof,
the p-type semiconductor layer comprises one material of a tellurium (Te)-based material, a tellurium oxide (TeOx)-based material, a selenium (Se)-based material, a copper oxide (CuO)-based material, a tin oxide (SnO)-based material, a nickel oxide (NiOx)-based material, and a combination of at least two materials thereof.
7 . The complementary TFT of claim 1 , wherein the second TFT comprises:
a gate insulation layer disposed on the second gate electrode layer;
a second source electrode layer and a second drain electrode layer disposed on the gate insulation layer;
a metal pad disposed in a same layer as the second source electrode layer and the second drain electrode layer and electrically connected with the second gate electrode layer; and
a second conductive semiconductor layer disposed on the second source electrode layer and the second drain electrode layer.
8 . The complementary TFT of claim 7 , wherein the metal pad of the second TFT is connected with the second gate electrode layer.
9 . The complementary TFT of claim 7 , wherein the second conductive semiconductor layer is disposed on an upper surface and a side surface of the second source electrode layer and an upper surface and a side surface of the second drain electrode layer.
10 . The complementary TFT of claim 7 , wherein the first conductive semiconductor layer of the first TFT is disposed coplanar with the second gate electrode layer of the second TFT.
11 . A method of manufacturing a complementary thin film transistor (TFT) including a first TFT and a second TFT, the method comprising:
forming a first conductive semiconductor layer of the first TFT and a second gate electrode layer of the second TFT on a substrate;
forming a gate insulation layer on the first conductive semiconductor layer and the second gate electrode layer;
forming a first gate electrode layer, a first source electrode layer, and a first drain electrode layer of the first TFT on the gate insulation layer, and simultaneously, forming a second source electrode layer and a second drain electrode layer of the second TFT and a metal pad, that is connected with the second gate electrode layer, on the gate insulation layer; and
forming a second conductive semiconductor layer electrically connected with the second source electrode layer and the second drain electrode layer,
wherein the first conductive semiconductor layer and the second gate electrode layer comprise a same material.
12 . The method of claim 11 , wherein the forming of the first conductive semiconductor layer of the first TFT and the second gate electrode layer of the second TFT comprises simultaneously forming the first conductive semiconductor layer and the second gate electrode layer in a same layer by using one deposition process.
13 . The method of claim 11 , wherein the first conductive semiconductor layer is an n-type semiconductor layer or a p-type semiconductor layer,
when the first conductive semiconductor layer is the n-type semiconductor layer, the second gate electrode layer comprises the same material as a material of the n-type semiconductor layer, and
when the first conductive semiconductor layer is the p-type semiconductor layer, the second gate electrode layer comprises the same material as a material of the p-type semiconductor layer.
14 . The method of claim 11 , wherein the substrate is a non-silicon substrate having a low heat resistance temperature, and
the non-silicon substrate is a glass substrate including quartz or sapphire.
15 . A pixel structure comprising:
a substrate;
a switch thin film transistor (TFT) structure and a driving TFT structure disposed on the substrate;
a passivation layer covering the switch TFT structure and the driving TFT structure;
a pixel electrode layer disposed on the passivation layer and electrically connected with a source electrode layer of the driving TFT through a contact hole formed in the passivation layer; and
an organic light emitting diode (OLED) layer disposed on the pixel electrode layer,
wherein a first conductive semiconductor layer of the switch TFT structure and a gate electrode layer of the driving TFT structure are disposed in a same layer and include a same material,
wherein the driving TFT structure includes:
a gate insulation layer disposed on the gate electrode layer;
a source electrode layer and a drain electrode layer disposed on the gate insulation layer;
a metal pad layer electrically connected with the gate electrode layer; and
a second conductive semiconductor layer disposed on the source electrode layer and the drain electrode layer.
16 . The pixel structure of claim 15 , wherein, when the first conductive semiconductor layer is an n-type semiconductor layer, the gate electrode layer comprises the same material as a material of the n-type semiconductor layer, and
when the first conductive semiconductor layer is a p-type semiconductor layer, the gate electrode layer comprises the same material as a material of the p-type semiconductor layer.
17 . The pixel structure of claim 15 , wherein the first conductive semiconductor layer is a channel layer on which impurities are not doped.
18 . The pixel structure of claim 15 , wherein the first conductive semiconductor layer and the gate electrode layer are simultaneously formed by one process.
19 . The pixel structure of claim 15 , wherein the first conductive semiconductor layer of the switch TFT structure is disposed coplanar with the gate electrode layer of the driving TFT structure.