Semiconductor package and method of fabricating the same
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.
1 . A method of fabricating a semiconductor package, the method comprising:
providing a semiconductor substrate extending in a first direction and a second direction, perpendicular to the first direction, the semiconductor substrate having an active surface and an inactive surface that is opposite to the active surface;
forming a transistor on the active surface of the semiconductor substrate;
forming through vias in the semiconductor substrate, the through vias extending from the active surface into the semiconductor substrate, the through vias each including a first end that faces the inactive surface and is covered by a corresponding portion of the semiconductor substrate;
then, forming a first pad layer on the active surface of the semiconductor substrate;
then, performing a first planarization process comprising planarizing the first pad layer including removing material from the first pad layer;
then, thinning the semiconductor substrate by performing on the inactive surface of the semiconductor substrate a thinning process including removing semiconductor material from the inactive surface to uncover and expose the first ends of each of the through vias;
then, forming a second pad layer on the inactive surface of the semiconductor substrate;
then, performing a second planarization process comprising planarizing the second pad layer including removing material from the second pad layer; and
after the second planarization process, performing a third planarization process comprising planarizing the first pad layer including removing material from the first pad layer.
2 . The method of claim 1 , wherein the first pad layer includes:
first pads; and
a first passivation layer that surrounds the first pads and exposes one surface of each of the first pads,
wherein, after the third planarization process, a first surface of the first passivation layer is flat, the first surface being opposite to the semiconductor substrate.
3 . The method of claim 2 , wherein a second surface of the first passivation layer is uneven, the second surface facing the semiconductor substrate.
4 . The method of claim 2 , wherein, after the third planarization process, a thickness, in a third direction perpendicular to the first direction and the second direction, of the first passivation layer is changed based on position along the first direction.
5 . The method of claim 4 , wherein a deviation between maximum and minimum values of the thickness of the first passivation layer is in a range of about 50 Å to about 500 Å.
6 . The method of claim 2 , wherein the second pad layer includes:
second pads; and
a second passivation layer that surrounds the first pads and exposes one surface of each of the first pads,
wherein, after the second planarization process, a third surface of the second passivation layer is flat, the third surface being opposite to the semiconductor substrate.
7 . The method of claim 2 , further comprising, before performing the third planarization process, forming an additional conductive layer on the first pad layer,
wherein the additional conductive layer is connected to first pads on the first pad layer, and
wherein the additional conductive layer and the first pads are formed of the same material.
8 . The method of claim 7 , further comprising, before performing the third planarization process, forming an additional dielectric layer on the first pad layer,
wherein the additional dielectric layer is connected to a first passivation layer of the first pad layer, and
wherein the additional dielectric layer and the first passivation layer of the first pad layer are formed of the same material.
9 . The method of claim 1 , wherein the thinning process causes the semiconductor substrate and the first pad layer to have a wavy shape.
10 . The method of claim 1 ,
wherein performing the third planarization process includes:
fixing the semiconductor substrate inside a ring frame that surrounds the semiconductor substrate; and
performing a chemical mechanical polishing (CMP) process on the semiconductor substrate and the ring frame, or
wherein performing the third planarization process includes:
attaching the semiconductor substrate to a carrier substrate;
performing a chemical mechanical polishing (CMP) process on the semiconductor substrate; and
removing the carrier substrate.
11 . The method of claim 1 , wherein forming the first pad layer includes:
before the thinning process, forming on the semiconductor substrate a first passivation layer that has openings; and
forming on the first passivation layer a conductive layer that fills the openings; and
performing a separation process to separate the conductive layer into discrete first pads in the openings.
12 . The method of claim 11 , wherein
the conductive layer is formed before performing the thinning process, and
the separation process of the conductive layer is performed by using the first planarization process or the third planarization process.
13 . The method of claim 11 , wherein
the conductive layer is formed after the thinning process is performed, and
the separation process of the conductive layer is performed by using the third planarization process.
14 . A method of fabricating a semiconductor package, the method comprising:
providing a semiconductor substrate extending in a first direction and a second direction, perpendicular to the first direction;
forming a semiconductor element on an active surface of the semiconductor substrate;
forming first pads on the active surface of the semiconductor substrate and a first passivation layer that surrounds the first pads and exposes one surface of each of the first pads;
performing a first planarization process comprising planarizing the first pads and planarizing the first passivation layer including removing material from the first pads and the first passivation layer;
performing a thinning process to the semiconductor substrate comprising thinning by removing material from an inactive surface of the semiconductor substrate;
performing a second planarization process comprising planarizing the inactive surface of the semiconductor substrate including removing material from the semiconductor substrate; and
performing a third planarization process comprising planarizing the first pads and the first passivation layer including material from the first pads and first passivation layer,
wherein, after the third planarization process, a thickness, in a third direction perpendicular to the first direction and the second direction, of the first passivation layer is changed based on position along the first direction.
15 . The method of claim 14 , wherein, after the third planarization process, a first surface of the first passivation layer is flat, the first surface being opposite to the semiconductor substrate.
16 . The method of claim 15 , wherein a second surface of the first passivation layer is uneven, the second surface facing the semiconductor substrate.
17 . The method of claim 14 , wherein a deviation between maximum and minimum values of the thickness of the first passivation layer is in a range of about 50 Å to about 500 Å.
18 . The method of claim 14 , further comprising, before the second planarization process, forming second pads on the inactive surface of the semiconductor substrate and a second passivation layer that surrounds the second pads and exposes one surface of each of the second pads,
wherein the second planarization process is performed on the second pads and the second passivation layer, and
wherein, after the second planarization process, a third surface of the second passivation layer is flat, the third surface being opposite to the semiconductor substrate.
19 . The method of claim 14 , wherein the thinning process causes the semiconductor substrate to have a wavy shape.
20 . The method of claim 14 , further comprising, before performing the third planarization process, forming an additional conductive layer or an additional dielectric layer on the first pads and the first passivation layer,
wherein the third planarization process exposes the first pads and the first passivation layer.