Granted Patent B2

US 12,644,926 · App. 18/727,581 · Granted Jun 2, 2026

Inventors: Runjiang Dou (Beijing, CN); Jingyi Yu (Tianjin, CN); Nanjian Wu (Beijing, CN); Liyuan Liu (Beijing, CN); Jian Liu (Beijing, CN)

Assignee: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES Beijing, China

G01R31/318314G01R31/31905G01R31/31908

Abstract

Claims (35)

1 . A data simulation apparatus, comprising:

a programmable logic device configured to implement at least one interface protocol, to send and receive simulation data and test data respectively according to the at least one interface protocol, wherein

the simulation data comprises first data and second data, and

a transmission rate of the first data is lower than a transmission rate of the second data;

at least one first interface configured to connect the programmable logic device and at least one first device under test, to transmit the first data and the test data;

at least one second interface configured to connect the programmable logic device and at least one second device under test, so as to transmit the second data and the test data,

a disk array connected to the programmable logic device in communication and configured to store the simulation data and the test data; and

a cache array connected to the programmable logic device in communication and configured to read and write data for the disk array;

wherein the disk array comprises at least one disk, the disk comprises at least one sending channel sector and at least one receiving channel sector, the sending channel sector is configured to store the sent simulation data, and the receiving channel sector is configured to store the received test data;

wherein the cache array comprises at least one cache element, the cache element comprises at least one sending channel buffer and at least one receiving channel buffer, the sending channel buffer is configured to read data from the sending channel sector, and the receiving channel buffer is configured to write data to the receiving channel sector; and

wherein each of the first interface and the second interface is allocated with an independent sending channel sector and an independent receiving channel sector.

2 . The data simulation apparatus according to claim 1 , wherein the sending channel buffer and the receiving channel buffer use ping-pong cache.

3 . The data simulation apparatus according to claim 1 , wherein the programmable logic device comprises an on-chip memory configured to read and write data for the cache array.

4 . The data simulation apparatus according to claim 1 ,

wherein the first interface comprises a low-voltage differential signaling interface, a universal asynchronous receiver/transmitter interface, and a CANBUS interface; and

wherein the second interface comprises a TLK2711 interface and an Ethernet interface.

5 . The data simulation apparatus according to claim 1 , further comprising:

a PCIe bus configured to connect the programmable logic device and a client, so as to transmit the simulation data;

wherein the programmable logic device is further configured to acquire configuration information through the PCIe bus, so as to divide the sending channel sector and the receiving channel sector;

wherein the disk further comprises:

an independent configuration sector configured to store the configuration information; and

wherein the cache element further comprises:

an independent buffer configured to read and write data for the independent configuration sector.

6 . The data simulation apparatus according to claim 5 , wherein the programmable logic device is further configured to acquire a configuration register through the PCIe bus to reset a first address of the sending channel sector or the receiving channel sector.

7 . The data simulation apparatus according to claim 5 , wherein the PCIe bus is connected to the client through a thunderbolt controller.

8 . The data simulation apparatus according to claim 1 , wherein the first interface or the second interface uses any one of single-frame synchronous mode, single-frame asynchronous mode, continuous synchronous mode and continuous asynchronous mode to transmit the simulation data.

9 . A data simulation method, comprising:

using a programmable logic device to implement at least one interface protocol;

acquiring an interface configuration information according to the interface protocol;

using at least one first interface and at least one second interface to transmit simulation data and test data according to the interface configuration information; and

reading and writing on the simulation data and test data using a cache array and a disk array;

wherein the simulation data comprises first data and second data, and a transmission rate of the first data is lower than a transmission rate of the second data,

wherein the disk array comprises at least one disk, the disk comprises at least one sending channel sector and at least one receiving channel sector, the sending channel sector is configured to store the sent simulation data, and the receiving channel sector is configured to store the received test data;

wherein the cache array comprises at least one cache element, the cache element comprises at least one sending channel buffer and at least one receiving channel buffer, the sending channel buffer is configured to read data from the sending channel sector, and the receiving channel buffer is configured to write data to the receiving channel sector; and

wherein each of the first interface and the second interface is allocated with an independent sending channel sector and an independent receiving channel sector.

Assignments (1)

Continuity (1)

References Cited (15)