Efficient memory operation using a destructive read memory array
A system may include a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction. A system may include a controller configured to erase the data from the memory by commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite of the first direction and skipping a subsequent write operation of a null value to the memory.
1 . A system comprising:
a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction;
a data bus; and
a controller communicatively coupled to the memory by the data bus and configured to:
operate the data bus in a read-mode of operation;
while operating the data bus in the read-mode of operation, erase the data from the memory by:
commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite to the first direction; and
skipping a subsequent write operation of a null value to the memory; and
maintain the data bus in the read-mode of operation for one or more read requests until a write request is received.
2 . The system of claim 1 , wherein the ferroelectric capacitor includes a ferroelectric layer positioned between a top conductive plate and a bottom conductive plate, and wherein the first direction includes the electric polarization of the ferroelectric layer from the top conductive plate toward the bottom conductive plate in response to applying a supply voltage to the top conductive plate.
3 . The system of claim 2 , wherein commanding the electric polarization of the ferroelectric capacitor in the second direction, opposite to the first direction, includes commanding a voltage pulse of the supply voltage at the bottom conductive plate, and wherein the second direction includes the electric polarization of the ferroelectric layer from the bottom conductive plate toward the top conductive plate in response to the voltage pulse.
4 . The system of claim 1 , further comprising a sense amplifier, and wherein the controller is further configured to read data from the memory by:
reading stored data of the first logic state from the sense amplifier in response to the sense amplifier detecting a current pulse during application of an electric field to the ferroelectric capacitor in the second direction; and
reading stored data of a second logic state from the sense amplifier in response to the sense amplifier not detecting the current pulse during application of the electric field to the ferroelectric capacitor in the second direction.
5 . The system of claim 1 , further comprising a processor executing an operating system, and wherein the controller is configured to erase the data from the ferroelectric capacitor in response to a memory reclamation request from the operating system.
6 . The system of claim 1 , wherein the one or more read requests include a read request at another memory location, and the controller is further configured to perform operations comprising:
executing the read request while operating the data bus in the read-mode of operation, without switching the data bus to a write-mode of operation after erasing the data from the memory and before executing the read request.
7 . The system of claim 1 , wherein the memory is a cache line of a last-level cache, and wherein the controller is configured to erase the data from the memory in response to a cache line invalidation request.
8 . The system of claim 1 , wherein the memory is a memory cell of a ferroelectric random-access memory array.
9 . The system of claim 1 , wherein to maintain the data bus in the read-mode of operation for the one or more read requests until the write request is received, the controller is further configured to:
continue operating the data bus in the read-mode of operation without switching the data bus to a write-mode of operation after erasing the data from the memory and before receiving the one or more read requests.
10 . A system comprising:
a capacitor configured to be in one of a set state where the capacitor stores data and a reset state where the capacitor stores a null value based on a polarization direction of a ferroelectric layer of the capacitor;
a data bus; and
a controller communicatively coupled to the data bus and configured to perform operations comprising:
receiving a request to erase the data from the capacitor while the capacitor is in the set state; and
in response to receiving the request:
operating the data bus in a read-mode of operation;
causing a reversal of the polarization direction to transition the capacitor to the reset state without performing a write operation of the null value to the capacitor; and
continuing to operate the data bus in the read-mode of operation after transitioning the capacitor to the reset state until a write request is received.
11 . The system of claim 10 , wherein:
the ferroelectric layer is positioned between a top conductive plate that is electrically connected to a bitline via a transistor and a bottom conductive plate;
the polarization direction of the ferroelectric layer in the set state is created via a supply voltage being applied to the top conductive plate while biasing the bottom conductive plate at a reference voltage; and
the polarization direction of the ferroelectric layer in the reset state is created via the supply voltage being applied to the bottom conductive plate while biasing the top conductive plate at a reference voltage.
12 . The system of claim 10 , wherein the ferroelectric layer is positioned between a top conductive plate that is electrically connected to a bitline via a transistor and a bottom conductive plate, and wherein causing the reversal of the polarization direction to transition the capacitor to the reset state without performing the write operation of the null value to the capacitor includes:
commanding, by the controller, a voltage pulse to be applied to the bottom conductive plate while biasing the top conductive plate at a reference voltage; and
not commanding, by the controller, a subsequent voltage pulse to be applied to the top conductive plate while biasing the bottom conductive plate at the reference voltage.
13 . The system of claim 10 , wherein the polarization direction of the ferroelectric layer is in a first direction during the reset state and is in a second direction, opposite to the first direction, during the set state, and wherein causing the reversal of the polarization direction to transition the capacitor to the reset state without performing the write operation of the null value to the capacitor includes:
commanding, by the controller, application of an electric field across the ferroelectric layer in the first direction; and
not commanding, by the controller, a subsequent application of the electric field across the ferroelectric layer in the second direction.
14 . The system of claim 13 , wherein the controller is further configured to perform operations comprising:
receiving, as the write request, a request to store new data in the capacitor while the capacitor is in the reset state; and
in response to receiving the write request:
operating the data bus in a write-mode of operation; and
causing the polarization direction of the ferroelectric layer to change from the first direction to the second direction.
15 . The system of claim 10 , wherein the controller is further configured to perform operations comprising:
receiving a read request for another memory location while continuing to operate the data bus in the read-mode of operation after transitioning the capacitor to the reset state; and
executing the read request while operating the data bus in the read-mode of operation, without switching the data bus to a write-mode of operation after transitioning the capacitor to the reset state and before executing the read request.
16 . A method comprising:
receiving, at a controller, a request to erase data at a memory location that stores the data using a ferroelectric capacitor;
commanding, by the controller, a read operation of the memory location to generate a null value at the memory location without an associated null value write operation to the memory location to erase the data at the memory location;
operating a data bus in a read-mode of operation while generating the null value at the memory location; and
continuing to operate the data bus in the read-mode of operation for one or more read requests until a write request is received.
17 . The method of claim 16 , wherein the ferroelectric capacitor includes a ferroelectric layer positioned between a top conductive plate and a bottom conductive plate, and the read operation comprises:
commanding a voltage pulse at the bottom conductive plate via a bitline while biasing the top conductive plate at a reference voltage via a control gate of a transistor; and
sensing a voltage differential across the ferroelectric layer via a sense amplifier electrically connected to the bitline.
18 . The method of claim 17 , wherein sensing the voltage differential further comprises:
identifying, via the sense amplifier, a first logic state at the memory location in response to detecting a current pulse at the bitline; or
identifying, via the sense amplifier, a second logic state at the memory location in response to not detecting a current pulse at the bitline.
19 . The method of claim 16 , wherein the request to erase the data at the memory location is a memory reclamation request when the memory location is a main memory of a device or is a cache line invalidation request when the memory location is a cache line of the device.
20 . The method of claim 16 , wherein continuing to operate the data bus in the read-mode of operation for the one or more read requests until the write request is received comprises:
executing a read request at another memory location while operating the data bus in the read-mode of operation, without switching the data bus to a write-mode of operation after generating the null value and before executing the read request.