IP Library › Granted Patent US 12,645,393
Granted Patent B2
US 12,645,393 · App. 18/626,888 · Granted Jun 2, 2026

Write buffer extensions for storage interface controllers

Inventors: Sharath Chandra Ambula (Mancherial, IN); Sushil Kumar (Hyderabad, IN); Venkata Kiran Kumar Matturi (Khammam, IN)
Assignee: Micron Technology, Inc.
G06F3/0656G06F1/3275G06F3/0625G06F3/0647G06F3/0679
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Quick Facts
Patent No.
US 12,645,393
App. No.
18/626,888
Granted
Jun 2, 2026
Kind
B2
Abstract

Methods, systems, and devices for write buffer extensions for storage interface controllers are described. Apparatuses and methods are presented in which a buffer may be used to temporarily store data from an application if the memory device is in an INACTIVE power mode. This may allow the memory device to remain asleep. The buffer may be positioned on the host device so that the power mode of the memory device may not affect it. That way, data may be stored in the buffer without waking up the memory device. If the memory device is in an ACTIVE power mode, the data that has been temporarily stored in the buffer may be sent to the memory device for storage. During read operations, if the requested data is stored in the buffer, it may be used instead of data in the memory device.

Claims (67)

1 . A method, comprising:

receiving, by a storage interface controller of a host device, a plurality of data sets to write to a storage device;

determining, by the storage interface controller, a power mode of the storage device in response to receiving each respective data set of the plurality of data sets;

storing, by the storage interface controller, each respective data set to a write buffer in response to the determined power mode of the storage device being an inactive power mode;

refraining, by the storage interface controller, from waking up the storage device in response to the determined power mode of the storage device being the inactive power mode; and

sending, by the storage interface controller, each respective data set stored in the write buffer to the storage device in response to the power mode of the storage device being an active power mode.

2 . The method of claim 1 , wherein the plurality of data sets comprises a first data set, and wherein the method further comprises:

receiving a second data set to write to the storage device, the second data set exclusive of the plurality of data sets;

determining the power mode of the storage device based at least in part on receiving the second data set; and

based on the determined power mode of the storage device being the inactive power mode and an amount of data stored in the write buffer exceeding a threshold:

waking the storage device;

retrieving the first data set from the write buffer;

sending the first data set to the storage device;

sending the second data set to the storage device; and

putting the storage device back to sleep.

3 . The method of claim 1 , further comprising:

receiving a request to read a data set associated with an address of the storage device;

determining that the data set associated with the address is not stored in the write buffer;

retrieving the data set associated with the address from the storage device; and

sending the retrieved data set to the host device.

4 . The method of claim 3 , further comprising:

determining, upon receiving the request to read the data set, whether the power mode of the storage device is the inactive power mode;

waking the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode, wherein retrieving the data set associated with the address from the storage device is performed subsequent to waking up the storage device; and

commanding the storage device back to the inactive power mode subsequent to retrieving the data set associated with the address from the storage device.

5 . The method of claim 1 , wherein storing each respective data set to the write buffer is also based at least in part on an amount of additional data stored in the write buffer.

6 . The method of claim 1 , wherein the storage interface controller comprises a universal flash storage (UFS) controller.

7 . The method of claim 1 , wherein the storage device is physically separated from the storage interface controller.

8 . The method of claim 1 , wherein the write buffer is positioned on the storage interface controller.

9 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:

receive, by a storage interface controller of a host device, a plurality of data sets to write to a storage device;

determine, by the storage interface controller, a power mode of the storage device in response to receiving each respective data set of the plurality of data sets;

store, by the storage interface controller, each respective data set of the plurality of data sets to a write buffer in response to the determined power mode of the storage device being an inactive power mode;

refrain, by the storage interface controller, from waking up the storage device in response to the determined power mode of the storage device being the inactive power mode; and

send, by the storage interface controller, stored data and each respective data set to the storage device in response to the determined power mode of the storage device being an active power mode.

10 . The non-transitory computer-readable medium of claim 9 , the plurality of data sets comprises a first data set, and wherein the instructions are further executable by the one or more processors to:

receive a second data set to write to the storage device, the second data set exclusive of the plurality of data sets;

determine the power mode of the storage device based at least in part on receiving the second data set; and

based on the determined power mode of the storage device being the inactive power mode and an amount of data stored in the write buffer exceeding a threshold:

wake the storage device;

retrieve the first data set from the write buffer;

send the first data set to the storage device;

send the second data set to the storage device; and

put the storage device back to sleep.

11 . The non-transitory computer-readable medium of claim 9 , wherein the instructions are further executable by the one or more processors to:

receiving a request to read a data set associated with an address of the storage device;

determining that the data set associated with the address is not stored in the write buffer;

retrieving the data set associated with the address from the storage device; and

sending the retrieved data set to the host device.

12 . The non-transitory computer-readable medium of claim 11 , wherein the instructions are further executable by the one or more processors to:

determining, upon receiving the request to read the data set, whether the power mode of the storage device is the inactive power mode;

waking up the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode, wherein retrieving the data associated with the address from the storage device is performed subsequent to waking up the storage device; and

commanding the storage device back to the inactive power mode subsequent to retrieving the data associated with the address from the storage device.

13 . The non-transitory computer-readable medium of claim 9 , wherein storing the data to the write buffer is also based at least in part on an amount of additional data stored in the write buffer.

14 . The non-transitory computer-readable medium of claim 9 , wherein the storage interface controller comprises a universal flash storage (UFS) controller.

15 . The non-transitory computer-readable medium of claim 9 , wherein the storage device is physically separated from the storage interface controller.

16 . The non-transitory computer-readable medium of claim 9 , wherein the write buffer is positioned on the storage interface controller.

17 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:

receive, by a storage interface controller of a host device, data to write to a storage device;

determine, by the storage interface controller upon receiving the data, whether a power mode of the storage device is an inactive power mode;

store, by the storage interface controller, the data to a write buffer of the storage interface controller, based at least in part on determining that the power mode of the storage device is the inactive power mode;

refrain from waking up the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode;

retrieve, by the storage interface controller from the write buffer, the data based at least in part on a change to the power mode of the storage device; and

send, by the storage interface controller, the data to the storage device.

18 . The non-transitory computer-readable medium of claim 17 , wherein moving the data from the write buffer to the storage device comprises:

determining, by the storage interface controller, whether the power mode of the storage device has changed to an active power mode; and

moving, by the storage interface controller, the data from the write buffer to the storage device based at least in part on determining that the power mode of the storage device has changed to the active power mode.

19 . The non-transitory computer-readable medium of claim 17 , wherein storing the data to the write buffer is also based at least in part on an amount of additional data stored in the write buffer.

Continuity (3)
Continuation 17807838 · Jun 20, 2022
Provisional Application 63277354 · Nov 9, 2021
Related Publication 20240319914A1 · Sep 26, 2024
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