Memory system for secure read and write operations based on predefined data patterns
A memory buffer device facilitates secure read and write operations associated with data that includes a predefined data pattern. For read operations, the memory buffer device detects a read data pattern in the read data that matches a predefined data pattern. The memory buffer device may then generate a read response that includes metadata identifying the read data pattern without sending the read data itself. The memory buffer device may also receive Write Request without Data (RwoD) commands from the host that include metadata identifying a write data pattern. The memory buffer device identifies the associated data pattern and writes the data pattern or the metadata to the memory array. The memory buffer device may include encryption and decryption logic for communicating the metadata in encrypted form.
1 . A memory buffer device, comprising:
a host-side interface to receive, from a host device via a packetized serial communication link, a host-side read command including a read memory address and to output a read response to the host device via the packetized serial communication link;
a memory-side interface to communicate with a memory device, the memory-side interface including a data interface and a command/address interface; and
a command controller to issue a memory-side read command including the read memory address to the memory device via the command/address interface, to receive output data from the memory device via the data interface in response to the memory-side read command, to determine if the output data corresponds to a read data pattern from a set of predefined data patterns, and to generate the read response for sending to the host device via the host-side interface as packetized serial communication data, wherein the read response includes read pattern metadata in a data packet header that identifies the read data pattern when the output data corresponds to the read data pattern, and wherein the read response includes the output data from the read memory address when the output data does not correspond to any of the set of predefined data patterns.
2 . The memory buffer device of claim 1 , wherein the read pattern metadata further identifies a length of the read data pattern.
3 . The memory buffer device of claim 1 , wherein the command controller comprises:
pattern detection logic to obtain the output data from the memory device associated with the memory-side read command, to compare the output data with the set of predefined data patterns, and to determine that the output data corresponds to the read data pattern responsive to detecting a match.
4 . The memory buffer device of claim 1 , wherein the command controller comprises:
metadata detection logic to obtain the output data from the memory device associated with the memory-side read command, to determine that the output data is formatted as read pattern metadata, and to determine that the output data corresponds to the read data pattern responsive to detecting that the output data is formatted as the read pattern metadata.
5 . The memory buffer device of claim 1 , wherein the command controller comprises:
a programming interface to receive programming data for programming the set of predefined data patterns; and
a pattern register for storing the set of predefined data patterns.
6 . The memory buffer device of claim 1 , wherein the memory buffer device further comprises:
encryption logic to encrypt at least a portion of the read response that identifies the read data pattern.
7 . The memory buffer device of claim 1 ,
wherein the host-side interface is further configured to receive, from the host device, a write-without-data command including a write memory address and write pattern metadata identifying a write data pattern from the set of predefined data patterns;
wherein the command controller is further configured to generate a memory write command to associate the write memory address with the write data pattern responsive to the write-without-data command; and
wherein the memory-side interface is further configured to issue the memory write command to the memory device.
8 . The memory buffer device of claim 7 , wherein the command controller comprises:
pattern generation logic to obtain the write data pattern corresponding to the write pattern metadata from a pattern register, and generate the memory write command to write the write data pattern to the write memory address.
9 . The memory buffer device of claim 7 , wherein the command controller comprises:
metadata generation logic to obtain the write pattern metadata from the write-without-data command, and generate the memory write command to write the write pattern metadata to the memory device in association with the write memory address.
10 . The memory buffer device of claim 7 , wherein the write pattern metadata further identifies a length of an address range associated with the write data pattern, and wherein the memory write command associates the address range with the write data pattern.
11 . The memory buffer device of claim 7 , wherein the memory buffer device further comprises:
decryption logic to decrypt at least the write pattern metadata of the write-without-data command that identifies the write data pattern.
12 . The memory buffer device of claim 1 , wherein the memory buffer device and the memory device are separate chips mounted to a printed circuit board.
13 . A memory module comprising:
a memory device including a memory array; and
a memory buffer device including:
a host-side interface to receive, from a host device via a packetized serial communication link, a host-side read command including a read memory address and to output a read response to the host device via the packetized serial communication link;
a memory-side interface to communicate with the memory device, the memory-side interface including a data interface and a command/address interface; and
a command controller to issue a memory-side read command including the read memory address to the memory device via the command/address interface, to receive output data from the memory device via the data interface in response to the memory-side read command, to determine if the output data corresponds to a read data pattern from a set of predefined data patterns, and to generate the read response for sending to the host device via the host-side interface as packetized serial communication data, wherein the read response includes read pattern metadata in a data packet header that identifies the read data pattern when the output data corresponds to the read data pattern, and wherein the read response includes the output data from the read memory address when the output data does not correspond to any of the set of predefined data patterns.
14 . The memory module of claim 13 , wherein the host-side interface comprises a serial communication link for sending packetized commands and data between the memory module and the host device.
15 . A method for operating a memory buffer device, comprising:
receiving, via a host-side interface from a host device via a packetized serial communication, a host-side read command including a read memory address;
issuing from a command controller to a memory device via a command/address interface of a memory-side interface, a memory-side read command including the read memory address;
receiving output data in response to the memory-side read command from the memory device via a data interface of the memory-side interface;
determining, by the command controller, if the output data corresponds to a read data pattern from a set of predefined data patterns;
generating a read response for sending to the host device via the host-side interface as packetized serial communication data, wherein the read response includes read pattern metadata in a data packet header that identifies the read data pattern when the output data corresponds to the read data pattern, and wherein the read response includes the output data from the read memory address when the output data does not correspond to any of the set of predefined data patterns; and
outputting the read response to the host device via the host-side interface and the packetized serial communication link.
16 . The method of claim 15 , wherein the read pattern metadata further identifies a length of the read data pattern.
17 . The method of claim 15 , wherein outputting the read responses comprises:
encrypting at least a portion of the read response that identifies the read data pattern.